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| 型号： | IRDCIP1203-A |
| 厂商： | International Rectifier |
| 文件页数： | 12/23页 |
| 文件大小： | 0K |
| 描述： | IP1203 REFERENCE DESIGN KIT |
| 标准包装： | 1 |
| 系列： | iPOWIR™ |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 1.8V |
| 电流 - 输出： | 15A |
| 输入电压： | 5.5 ~ 13.2 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 400kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | iP1203 |
| 相关产品： | IP1203TRPBF-ND - IC REG BUCK SYNC ADJ 15A 24LGA IP1203PBF-ND - IC REG BUCK SYNC ADJ 15A 24LGA IP1203TR-ND - IC REG BUCK SYNC ADJ 15A 24LGA IP1203-ND - IC REG BUCK SYNC ADJ 15A 24LGA |
| 其它名称： | *IRDCIP1203-A |
iP1203
iP1203 Design Procedure
Only a few external components are required to com-
plete a dual output synchronous buck power supply
using iP1203. The following procedure will guide the
designer through the design and selection process
of these external components.
A typical application for the iP1203 is:
V IN = 12V, V OUT = 1.5V, I OUT = 15A, f sw = 300kHz, V p-p =
= 50mV
Setting the Output Voltage
The output voltage of the iP1203 is set by the 0.8V
reference V REF and external voltage dividers.
V ou t
R2
Setting the Overvoltage Trip
The output of the iP1203 will shut down if it experi-
ences a voltage in the range of 115% of V OUT . The
overvoltage sense pin FB s is connected to the out-
put through voltage dividers, R26 and R27 (Fig. 14),
and the trip setpoint is programmed according to
equation (1). A separate overvoltage sense pin FB s
is provided to protect the power supply output if for
some reason the main feedback loop is lost (for in-
stance, loss of feedback resistors). An optional 100pF
capacitor (C14) is used for delay and filtering.
If this redundancy is not required and if a Type II con-
trol loop compensation scheme is utilized, FB s pin
can be connected to FB.
Selecting the Soft-Start Capacitor
The soft start capacitor C ss is selected according to
equation (2):
FB
R5
t ss = 40 x C ss
(2)
S
iP1203
FB
C14
(Optional)
R26
R27
where,
t ss is the output voltage ramp time in milliseconds,
and C ss is the soft start capacitor in μ F.
A 0.1 μ F capacitor will provide an output voltage ramp-
up time of about 4ms.
Fig. 14: Typical Scheme for Output Voltage Setting
For Type II compensation,
Input Capacitor Selection
The switching currents impose RMS current require-
ments on the input capacitors. Equation (3) allows
the selection of the input capacitors.
V OUT is set according to equation (1):
I RMS = I out D ( 1 ? D )
(3)
V OUT = V REF x (1 + R 2 /R 5 ) (see Fig. 14)
(1)
where, I out is the output current, and D is the duty
cycle and is expressed as:
Setting R 2 to 1K, V OUT to 1.5V and V REF to 0.8V, will
result in R 5 = 1.14 Kohms. Final values can be se-
lected according to the desired accuracy of the out-
put.
To set the output voltage for Type III compensation,
refer to equation (24) in Type III compensation sec-
tion.
12
D = V OUT / V IN .
For the above example D= 0.13 and, using equation
(3) the capacitor rms current yields 5.0A.
www.irf.com
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