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参数资料
| 型号： | IRM7001 |
| 厂商： | Vishay Intertechnology,Inc. |
| 英文描述： | SIR Modulator/Demodulator |
| 中文描述： | 爵士调制/解调器 |
| 文件页数： | 6/11页 |
| 文件大小： | 531K |
| 代理商： | IRM7001 |
Document Number: 82576
Revision 17-August-01
www.vishay.com
6
Table 6. Operating Conditions at V
CC
Symbol
=5.5 V
IRDA Parameters
1. The Max Clk Frequency (f16xClk) represents the maximum
clock frequency that the IRM7001 internal state machine
should be driven at. Under normal circumstances, this clock
input should not exceed 16*115200(bps) =1.8432 MHz.
This is the maximum transmission rate under the IRDA Phys-
ical layer 1.0 specification. The IRM7001 can handle higher
clock rates, but the recommended maximum is as specified
above.
2. The Minimum Pulse Width (tmpw), represents the minimum
pulse width of the encoded IR_TXD pulse as well as the min-
imum pulse width for the IR_RCV pulse. As per the IRDA
specification, the minimum pulse width of the IR_TXD and
IR_RCV pulses should be 3*(1/1.8432 MHz) = 1.63
minimum pulse width that can be handled by the IRM7001 is
250ns, which is within the IRDA SIR specifications. Under
normal circumstances using a 16XCLK clock that does not
exceed 2 MHz, the minimum pulse width of IR_TXD should
not be shorter than 1.63 μs.
μ
S. The
Parameter
Min
Typ
Max
Unit
Conditions
Supply voltage
V
CC
2.7
5
5.5
V
Input voltage
V
IN
0
V
CC
V
Ambient temperature
Ta
–20
+85
°C
High-Level Input Voltage
V
IH
0.7 V
CC
V
CC
V
Low-Level Input Voltage
V
IL
0
0.3 V
CC
V
Output High Voltage
V
OH
4.5
V
I
OH
=2.0 mA
Output Low Voltage
V
OL
0.5
V
I
OL
=2.0 mA
Static Power Dissipation
P
STAT
0.44
0.61
mW
Dynamic Power Dissipation
P
DYN
11
16.5
mW
Static Current Consumption
I
STAT
80
110
μ
A
Dynamic Power Dissipation
I
DYN
2
3
mA
Max Clk Frequency(16XCLK)
f
16xclk
2
MHz
Minimum Pulse Width(IR_TXD)
t
mpw
1630
ns
Pulse Width on monoshot (IR_TXD)
t
mpw
1630
1710
1730
ns
Output Capacitance on Output Pads
used for simulation
C
OUT
50
pF
Value of pulldown resistor used on
POWERDN & PULSEMOD input pins
R
DWN
114
152
256
KOhms
Trigger Low Level Input Voltage
(For /NRST input pin)
VIL_TRIG
0.7
0.8
0.9
V
Trigger High Level Input Voltage
(For /NRST input pin)
VIH_TRIG
1.7
1.85
1.9
V
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