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参数资料
| 型号： | IRMD22381Q |
| 厂商： | International Rectifier |
| 文件页数： | 26/30页 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO IR22381Q MOTOR DRIVER |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电机控制 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | IR22381Q / IR22381Q |
| 主要属性： | 3 相，ACIM / BLAC，25 A 时为 380 V，带制动器，具有 1200V DC 总线功能 |
| 次要属性： | 与 ECONO2-PIM IGBT 模块兼容 |
| 已供物品： | 板 |
| 相关产品： | IR22381QPBF-ND - IC IGBT DRIVER 3PHASE 64-MQFP |
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IR22381Q PBF /IR21381Q ( P b F )
Sizing the turn-off gate resistor
The worst case in sizing the turn-off resistor R Goff is
when the collector of the IGBT in off state is forced
to commutate by external events (i.e. the turn-on of
As a result, when τ is faster than the collector rise
time (to be verified after calculation) the transfer
function can be approximated by:
= s ? ( R Goff + R DRn ) ? C RESoff
So that V ge = ( R Goff + R DRn ) ? C RESoff ?
V th > V ge = ( R Goff + R DRn ) ? C RESoff
the companion IGBT).
In this case the dV/dt of the output node induces a
parasitic current through C RESoff flowing in R Goff and
R DRn (see Figure 26).
If the voltage drop at the gate exceeds the threshold
voltage of the IGBT, the device may self turn on
causing large oscillation and relevant cross
conduction.
V ge
V de
time domain.
Then the condition:
dV de
dt
dV out
dt
in the
HS Turning ON
C RESoff
dV/dt
must be verified to avoid spurious turn on.
Rearranging the equation yields:
ON
R DRn
R Goff
C IES
OFF
(1)
R Goff <
V th
C RESoff
?
dV
dt
? R DRn
In any case, the worst condition for a spurious turn
Figure 26: R Goff sizing: current path when Low
Side is off and High Side turns on
on is with very fast steps on IGBT collector.
In that case collector to gate transfer function can
be approximated with the capacitor divider:
The transfer function between IGBT collector and
IGBT gate then becomes:
V ge = V de ?
C RESoff
( C RESoff + C IES )
V ge
V de
=
s ? ( R Goff + R DRn ) ? C RESoff
1 + s ? ( R Goff + R DRn ) ? ( C RESoff + C IES )
which is driven only by IGBT characteristics.
As an example, table 3 reports R Goff (calculated with
the above mentioned equation (1)) for two popular
Which yields to a high pass filter with a pole at:
IGBTs to withstand dV out /dt = 5V/ns .
1 / τ =
( R Goff
1
+ R DRn ) ? ( C RESoff + C IES )
NOTICE: the above-described equations are
intended being an approximated way for the gate
resistances sizing. More accurate sizing may
account more precise device modelling and
parasitic component dependent on the PCB and
power section layout and related connections.
Table 1: R Gon sizing driven by t sw constraint
IGBT
GB15XP120K*
GB05XP120K
IRGB5B120KD
Qge
12nC
3.7nC
3.7nC
Qgc
46nC
14nC
13nC
Vge*
9V
9.5V
9.5V
tsw
500ns
400ns
500ns
Iavg
116mA
44mA
33mA
Rtot
77 ?
124 ?
164 ?
RGon → std commercial value
Rtot - RDRp = 15 ? → 10 ?
Rtot - RDRp = 65 ? → 68 ?
Rtot - RDRp = 102 ? → 100 ?
Tsw
→ 465ns
→ 408ns
→ 502ns
Table 2: Table 2: RGon sizing driven by dVOUT/dt constraint
IGBT
GB15XP120K*
GB05XP120K
IRGB120KD
Qge
12nC
3.7nC
3.7nc
Qgc
46nC
14nC
13nC
Vge*
9V
9.5V
9.5V
CRESoff
38pF
12pF
11pF
Rtot
47 ?
91 ?
100 ?
RGon → std commercial value
Rtot - RDRp = 4.5 ? → 4.7 ?
Rtot - RDRp = 48.8 ? → 47 ?
Rtot - RDRp = 57 ? → 56 ?
dVout/dt
→ 5V/ns
→ 5.1V/ns
→ 5V/ns
26
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