参数资料
型号: IRPLDIM3
厂商: International Rectifier
文件页数: 14/27页
文件大小: 0K
描述: KIT DES FLUOR BALLAST IRS2158D
标准包装: 1
主要目的: 照明,镇流器控制
嵌入式:
已用 IC / 零件: IRS2158D
主要属性: 28W TL5,可调光,PFC,灯开路、使用寿命结束和断电保护
次要属性: 点火预热
已供物品: 板,CD
相关产品: IRS2158DSPBF-ND - IC DVR HALF BRIDGE 600V 16-SOIC
IRS2158DPBF-ND - IC DVR HALF BRIDGE 600V 16-PDIP
IRS2158DSTRPBF-ND - IC BALLAST CTRL 600V 16-SOIC
Regulated Lamp Current Control System
VCO
&
DRIVER
Error Amplifier
and Compensation
Reference
-
+
Lamp Arc Current
Fig 7. Closed Loop Dimming Control
The isolated 0 to 10 V control interface operates by means of a simple circuit, described in Design
Tip DT-02 . This operates in the same way as many other commercially available 0 to 10 V dimming
ballasts. The input internally biased at 10 V if nothing is connected and can be reduced to 0 V by sinking
current only. Isolation between the dimming input and the ballast circuitry is provided by means of an opto-
isolator (IC4) and an additional isolated winding of the PFC boost inductor LPFC.
This winding must be isolated from the other two windings and from the ferrite cores and should
be flash tested to 4 kV. In order to obtain sufficient voltage, this winding will need to have several more
turns than the zero current detection winding. It is necessary to ensure that the voltage across the 18 V
zener diode (D3) never falls below 18 V when the ballast output is dimmed and also over the range of line
supply voltage. The next part of the circuit, centered around the programmable unijunction transistor Q1,
generates an approximate ramp waveform across capacitor C7, which peaks at approximately 10 V
guaranteeing maximum output when 10 V input is applied at the dimming input.
A trigger voltage provided by a potential divider of 9 V is applied to the gate of Q1. C7 charges
through R15 until the voltage reaches a point one diode drop above the 9 V trigger voltage. Q1 then fires
and remains switched on until the current drops below the valley current of the device which is small,
discharging C7 again. This produces a continuously oscillating ramp waveform. It is important that R15 is
sufficiently large that it does not supply a current larger than the valley current, otherwise Q1 remains on
indefinitely and the circuit does not oscillate. It necessary for this oscillator to run at a frequency of several
hundred Hz to prevent it from being a source of visible flicker.
This sawtooth signal is fed into the inverting input of a comparator. Note that this circuit makes
use of a dual comparator IC by placing both comparators in parallel so as to provide greater current sinking
capability to drive the input of IC4. However, there is no need for this provided the comparator used is
capable of sinking the opto-isolator diode current, which in this case is around 13 mA. The opto-isolator
diode current should be chosen to be as low as possible to guarantee saturation of the transistor when it
sinks 1mA and consequently R14 is as large as possible. The non-inverting input is connected to the control
input and pulled high via R20, which provides a sink current of 1 mA. C8 removes any noise that may be
picked up at the comparator input.
The comparator output is open collector providing current to the input of IC4 when low. The diode
will be continuously off when the input is at maximum and on when it is zero. Hence the opto-isolator
output transistor will be fully on when the control voltage is at minimum and fully off when it is at
maximum, providing a reasonably linear change in the duty cycle at intermediate levels. It is important in
production to ensure that the opto-isolator used is rated to the correct voltage and has been certified to the
necessary safety standards. The transistor side of the opto-isolator has the emitter connected to 0 V (COM)
and the collector connected to the IRS2158D VCC supply of 15.6 V via a pull up resistor R22. The
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