参数资料
型号: IRS2332DSPBF
厂商: International Rectifier
文件页数: 15/39页
文件大小: 0K
描述: IC BRIDGE DVR 3PH 600V 28-SOIC
标准包装: 25
配置: 3 相桥
输入类型: 反相
延迟时间: 500ns
电流 - 峰: 250mA
配置数: 1
输出数: 3
高端电压 - 最大(自引导启动): 600V
电源电压: 10 V ~ 20 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
供应商设备封装: 28-SOIC W
包装: 管件
IRS233(0,2)(D)(S&J)PbF
Figure 10: Programming over-temperature protection
Figure 11: Using over-current protection and over-temperature
protection
Truth Table: Undervoltage lockout and ITRIP
Table 2 provides the truth table for the IRS233(0,2)(D). The first line shows that the UVLO for V CC has been tripped; the
FAULT output has gone low and the gate drive outputs have been disabled. V CCUV is not latched in this case and when V CC is
greater than V CCUV , the FAULT output returns to the high impedance state.
The second case shows that the UVLO for V BS has been tripped and that the high-side gate drive outputs have been disabled.
After V BS exceeds the V BSUV threshold, HO will stay low until the HVIC input receives a new falling transition of HIN. The third
case shows the normal operation of the HVIC. The fourth case illustrates that the ITRIP trip threshold has been reached and
that the gate drive outputs have been disabled and a fault has been reported through the fault pin. The fault output stays in the
low state until the fault condition has been removed by all LINx set to high state. Once the fault is removed, the voltage on the
FAULT pin will return to V CC .
VCC
VBS
ITRIP
FAULT
LO
HO
UVLO V CC
UVLO V BS
Normal operation
ITRIP fault
<V CCUV
15 V
15 V
15 V
---
<V BSUV
15 V
15 V
---
0V
0V
>V ITRIP
0
High impedance
High impedance
0
0
LIN
LIN
0
0
0
HIN
0
Table 2: IRS233(0,2)(D) UVLO, ITRIP & FAULT truth table
Advanced Input Filter
The advanced input filter allows an improvement in the input/output pulse symmetry of the HVIC and helps to reject noise
spikes and short pulses. This input filter has been applied to the HIN and LIN. The working principle of the new filter is shown
in Figures 12 and 13.
Figure 12 shows a typical input filter and the asymmetry of the input and output. The upper pair of waveforms (Example 1)
show an input signal with a duration much longer then t FIL,IN ; the resulting output is approximately the difference between the
input signal and t FIL,IN . The lower pair of waveforms (Example 2) show an input signal with a duration slightly longer then
t FIL,IN ; the resulting output is approximately the difference between the input signal and t FIL,IN .
Figure 13 shows the advanced input filter and the symmetry between the input and output. The upper pair of waveforms
(Example 1) show an input signal with a duration much longer then t FIL,IN ; the resulting output is approximately the same
duration as the input signal. The lower pair of waveforms (Example 2) show an input signal with a duration slightly longer
then t FIL,IN ; the resulting output is approximately the same duration as the input signal.
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