参数资料
型号: IS41C1664-30T
英文描述: 64K x 16 bit Dynamic RAM with EDO Page Mode
中文描述: 64K的× 16位动态随机存储器与江户页面模式
文件页数: 7/21页
文件大小: 219K
代理商: IS41C1664-30T
IC41C1664
IC41LV1664
Integrated Circuit Solution Inc.
DR033-0A 11/15/2001
7
ELECTRICAL CHARACTERISTICS
(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
Parameter
Test Condition
Speed
Min.
Max.
Unit
I
IL
Input Leakage Current
Any input 0V < V
IN
< Vcc
Other inputs not under test = 0V
–10
10
μA
I
IO
Output Leakage Current
Output is disabled (Hi-Z)
0V < V
OUT
< Vcc
–10
10
μA
V
OH
Output High Voltage Level
I
OH
= –5 mA
2.4
V
V
OL
Output Low Voltage Level
I
OL
= +4.2 mA
0.4
V
I
CC
1
Standby Current: TTL
RAS
,
LCAS
,
UCAS
> V
IH
Commerical
Commerical
5V
3.3V
2
1
mA
I
CC
2
Standby Current: CMOS
RAS
,
LCAS
,
UCAS
> V
CC
– 0.2V
5V
3.3V
1
mA
0.5
I
CC
3
Operating Current:
Random Read/Write
(2,3,4)
Average Power Supply Current
RAS
,
LCAS
,
UCAS
,
Address Cycling, t
RC
= t
RC
(min.)
-25
30
35
40
170
150
130
120
mA
I
CC
4
Operating Current:
EDO Page Mode
(2,3,4)
Average Power Supply Current
RAS
= V
IL
,
LCAS
,
UCAS
,
Cycling t
PC
= t
PC
(min.)
-25
30
35
40
170
150
130
120
mA
I
CC
5
Refresh Current:
RAS
-Only
(2,3)
Average Power Supply Current
RAS
Cycling,
LCAS
,
UCAS
> V
IH
t
RC
= t
RC
(min.)
-25
30
35
40
170
150
130
120
mA
I
CC
6
Refresh Current:
CBR
(2,3,5)
Average Power Supply Current
RAS
,
LCAS
,
UCAS
Cycling
t
RC
= t
RC
(min.)
-25
30
35
40
170
150
130
120
mA
Notes:
1. An initial pause of 200 μs is required after power-up followed by eight
RAS
refresh cycles (
RAS
-Only or CBR) before proper device
operation is assured. The eight
RAS
cycles wake-up should be repeated any time the t
REF
refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
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