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参数资料
| 型号： | IS42S16400B-7TL |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 1梅格位× 16位× 4银行（64兆位）同步动态RAM |
| 文件页数： | 10/55页 |
| 文件大小： | 472K |
| 代理商： | IS42S16400B-7TL |
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IS42S16400B
ISSI
10
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. D
02/10/05
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled
and READs or WRITEs with auto precharge disabled.
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been inter-
rupted by bank m’s burst.
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the
READ on bank n, CAS latency later (Consecutive READ Bursts).
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt
the READ on bank n when registered (READ to WRITE). DQM should be used one clock prior to the WRITE command to prevent
bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt
the WRITE on bank n when registered (WRITE to READ), with the data-out appearing CAS latency later. The last valid WRITE to
bank n will be data-in registered one clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt
the WRITE on bank n when registered (WRITE to WRITE). The last valid WRITE to bank n will be data-in registered one clock
prior to the READ to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the
READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Fig CAP 1).
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the
READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to bank m is registered (Fig CAP 2).
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the
WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after
t
WR
is met, where t
WR
begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered
one clock prior to the READ to bank m (Fig CAP 3).
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the
WRITE on bank n when registered. The PRECHARGE to bank n will begin after t
WR
is met, where t WR begins when the WRITE
to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Fig CAP 4).
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IS42S16400B-7TLI | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS42S16400B-7TLI-TR | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS42S16400B-7TL-TR | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS42S16400C1 | 制造商:ISSI 制造商全称:Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S16400C1-6T | 制造商:ISSI 制造商全称:Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
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