参数资料
型号: IS61DDB22M18-250M3
厂商: INTEGRATED SILICON SOLUTION INC
元件分类: DRAM
英文描述: 36 Mb (1M x 36 & 2M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs
中文描述: 2M X 18 DDR SRAM, 0.35 ns, PBGA165
封装: 15 X 17 MM, 1 MM PITCH, FBGA-165
文件页数: 7/25页
文件大小: 421K
代理商: IS61DDB22M18-250M3
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
2/22/05
7
ISSI
36 Mb (1M x 36 & 2M x 18)
DDR-II (Burst of 2) CIO Synchronous SRAMs
The
Timing Reference Diagram for Truth Table
on page
8
is helpful in understanding the clock and write truth
tables, as it shows the cycle relationship between clocks, address, data in, data out, and controls. All read
and write commands are issued at the beginning of cycle “t”.
State Diagram
Linear Burst Sequence Table
Burst Sequence
Case 1
Case 2
SA
0
SA
0
First Address
0
1
Second Address
1
0
Power Up
DDR
-II
Write
NOP
DDR
-II
Read
Write
Write
Notes:
1. Internal burst counter is fixed as two-bit linear; that is, when first address is A0+0, next internal burst address is A0+1.
2.
Read
refers to read active status with R/W = high.
3.
Write
refers to write active status with R/W = low.
4.
Load
refers to read new address active status with LD = low.
5.
Load
is read new address inactive status with LD = high.
Load New Address
Load
Load
Read
Load
Load
Load
Load
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