- 您现在的位置：买卖IC网 > PDF目录261234 > IS61LPS102418A-250B2I (INTEGRATED SILICON SOLUTION INC) 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM PDF资料下载
参数资料
| 型号： | IS61LPS102418A-250B2I |
| 厂商： | INTEGRATED SILICON SOLUTION INC |
| 元件分类： | SRAM |
| 英文描述： | 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| 中文描述： | 1M X 18 CACHE SRAM, 2.6 ns, PBGA119 |
| 封装： | 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119 |
| 文件页数： | 3/35页 |
| 文件大小： | 369K |
| 代理商： | IS61LPS102418A-250B2I |
第1页第2页当前第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页
Integrated Silicon Solution, Inc. — 1-800-379-4774
11
Rev. N
02/12/2010
IS61VPS25672A,IS61LPS25672A
IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A
TRUTH TABLE(1-8) (3CE option)
OPERATION
ADDRESS
CE
CE2
ZZ
ADSP
ADSP ADSC
ADSC
ADV
ADV WRITE
WRITE
OE
CLK
DQ
Deselect Cycle, Power-Down
None
H
X
L
X
L
X
L-H
High-Z
Deselect Cycle, Power-Down
None
L
X
L
XXXX
L-H
High-Z
Deselect Cycle, Power-Down
None
L
H
X
L
XXXX
L-H
High-Z
Deselect Cycle, Power-Down
None
L
X
L
H
L
X
L-H
High-Z
Deselect Cycle, Power-Down
None
L
H
X
L
H
L
X
L-H
High-Z
Snooze Mode, Power-Down
None
X
H
XXXXXX
High-Z
Read Cycle, Begin Burst
External
L
H
L
X
L
L-H
Q
Read Cycle, Begin Burst
External
L
H
L
X
H
L-H
High-Z
Write Cycle, Begin Burst
External
L
H
L
H
L
X
L
X
L-H
D
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
L-H
Q
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
L-H
High-Z
Read Cycle, Continue Burst
Next
X
L
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
X
L
H
L
H
L-H
High-Z
Read Cycle, Continue Burst
Next
H
X
L
X
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
H
X
L
X
H
L
H
L-H
High-Z
Write Cycle, Continue Burst
Next
X
L
H
L
X
L-H
D
Write Cycle, Continue Burst
Next
H
X
L
X
H
L
X
L-H
D
Read Cycle, Suspend Burst
Current
X
L
HHHH
L
L-H
Q
Read Cycle, Suspend Burst
Current
X
L
HHHHH
L-H
High-Z
Read Cycle, Suspend Burst
Current
H
X
L
X
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
H
X
L
X
HHHH
L-H
High-Z
Write Cycle, Suspend Burst
Current
X
L
H
L
X
L-H
D
Write Cycle, Suspend Burst
Current
H
X
L
X
H
L
X
L-H
D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For
WRITE, L means one or more byte write enable signals (BWa-h) and BWE are LOW or GW is LOW. WRITE = H for all
BWx, BWE, GW HIGH.
3.
BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and
DQPc.
BWd enables WRITEs to DQd’s and DQPd. BWe enables WRITEs to DQe’s and DQPe. BWf enables WRITEs to DQf’s
and DQPf.
BWg enables WRITEs to DQg’s and DQPg. BWh enables WRITEs to DQh’s and DQPh. DQPa-DQPh are avail-
able on the x72 version. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version.
4. All inputs except
OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation,
OE must be HIGH before the input data setup time and held HIGH during the
input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8.
ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
enable signals and
BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
相关PDF资料 |
PDF描述 |
|---|---|
| IS61LPS102418A-250B3 | 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| IS61LPS102418A-250B3I | 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| IS61LPS102418A-250TQ | 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| IS61LPS102418A-250TQI | 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| IS61LPS25672A-250B1 | 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IS61LPS102418A-250B3 | 功能描述:静态随机存取存储器 18Mb,Pipeline,Sync,1Mb x 18,250MHz,3.3V or 2.5V I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| IS61LPS102418A-250B3I | 功能描述:静态随机存取存储器 18Mb,Pipeline,Sync,1Mb x 18,250MHz,3.3V or 2.5V I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| IS61LPS102418A-250B3I-TR | 功能描述:静态随机存取存储器 18Mb,Pipeline,Sync,1Mb x 18,250MHz,3.3V or 2.5V I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| IS61LPS102418A-250B3-TR | 功能描述:静态随机存取存储器 18Mb,Pipeline,Sync,1Mb x 18,250MHz,3.3V or 2.5V I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| IS61LPS102418A-250TQ | 功能描述:静态随机存取存储器 18Mb,Pipeline,Sync,1Mb x 18,250MHz,3.3V or 2.5V I/O,100 Pin TQFP RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
发布紧急采购，3分钟左右您将得到回复。