参数资料
型号: IS62VV51216LL-70MI
厂商: INTEGRATED SILICON SOLUTION INC
元件分类: SRAM
英文描述: 512K X 16 STANDARD SRAM, 70 ns, PBGA48
封装: 7.20 X 8.70 MM, MINI, BGA-48
文件页数: 1/10页
文件大小: 87K
代理商: IS62VV51216LL-70MI
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
PRELIMINARY INFORMATION
Rev. 00B
01/10/01
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. Copyright 2000, Integrated Silicon Solution, Inc.
IS62VV51216LL
ISSI
512K x 16 LOW VOLTAGE, 1.8V ULTRA
LOW POWER CMOS STATIC RAM
FEATURES
High-speed access time: 70, 85 ns
CMOS low power operation
– 36 mW (typical) operating
– 9 W (typical) CMOS standby
TTL compatible interface levels
Single 1.65V-1.95V VCC power supply
Fully static operation: no clock or refresh
required
Three state outputs
Data control for upper and lower bytes
Industrial temperature available
Available in 48-pin mini BGA (7.2mm x 8.7mm)
DESCRIPTION
The
ISSI IS62VV51216LL is a high-speed, 8M bit static
RAMs organized as 512K words by 16 bits. It is fabricated
using
ISSI's high-performance CMOS technology. This
highly reliable process coupled with innovative circuit
design techniques, yields high-performance and low power
consumption devices.
For the IS62VV51216LL, when
CS1 is HIGH (deselected)
or when CS2 is LOW (deselected) or when
CS1 is LOW,
CS2 is HIGH and both
LB and UB are HIGH, the device
assumes a standby mode at which the power dissipation
can be reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(
WE) controls both writing and reading of the memory. A
data byte allows Upper Byte (
UB) and Lower Byte (LB)
access.
The IS62VV51216LL is packaged in the JEDEC standard
48-pin mini BGA (7.2mm x 8.7mm).
FUNCTIONAL BLOCK DIAGRAM
PRELIMINARY INFORMATION
DECEMBER 2000
A0-A18
CS1
OE
WE
512K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
CS2
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