参数资料
型号: IS62VV51216LL-70MI
厂商: INTEGRATED SILICON SOLUTION INC
元件分类: SRAM
英文描述: 512K X 16 STANDARD SRAM, 70 ns, PBGA48
封装: 7.20 X 8.70 MM, MINI, BGA-48
文件页数: 8/10页
文件大小: 87K
代理商: IS62VV51216LL-70MI
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
PRELIMINARY INFORMATION
Rev. 00B
01/10/01
IS62VV51216LL
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-70
-85
-100
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tWC
Write Cycle Time
70
85
100
ns
tSCS1
CS1 to Write End
60
70
80
ns
tAW
Address Setup Time to Write End
60
70
80
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Setup Time
0
0
0
ns
tPWB
LB, UB Valid to End of Write
60
70
80
ns
tPWE
WE Pulse Width
50
60
80
ns
tSD
Data Setup to Write End
30
35
40
ns
tHD
Data Hold from Write End
0
0
0
ns
tHZWE(3)
WE LOW to High-Z Output
20
25
30
ns
tLZWE(3)
WE HIGH to Low-Z Output
5
5
5
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4V to 1.4V and
output loading specified in Figure 1.
2. The internal write time is defined by the overlap of
CS1 LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the
CS1 and WE inputs and at least one
of the
LB and UB inputs being in the LOW state.
2. WRITE = (
CS1) [ (LB) = (UB) ] (WE).
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OE = HIGH or LOW)
DATA-IN VALID
DATA UNDEFINED
tWC
tSCS1
tSCS2
tAW
tHA
tPWE(4)
tHZWE
HIGH-Z
tLZWE
tSA
tSD
tHD
ADDRESS
CS1
CS2
WE
DOUT
DIN
LB, UB
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