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参数资料
| 型号： | IS80C52CXXX-12:D |
| 厂商： | TEMIC SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44 |
| 文件页数： | 25/134页 |
| 文件大小： | 3805K |
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120
8011Q–AVR–02/2013
ATmega164P/324P/644P
cleared by software (writing a logical one to the I/O bit location). For measuring frequency only,
the clearing of the ICFn Flag is not required (if an interrupt handler is used).
13.7
Output Compare Units
The 16-bit comparator continuously compares TCNTn with the Output Compare Register
(OCRnx). If TCNT equals OCRnx the comparator signals a match. A match will set the Output
Compare Flag (OCFnx) at the next timer clock cycle. If enabled (OCIEnx = 1), the Output Com-
pare Flag generates an Output Compare interrupt. The OCFnx Flag is automatically cleared
when the interrupt is executed. Alternatively the OCFnx Flag can be cleared by software by writ-
ing a logical one to its I/O bit location. The Waveform Generator uses the match signal to
generate an output according to operating mode set by the Waveform Generation mode
(WGMn3:0) bits and Compare Output mode (COMnx1:0) bits. The TOP and BOTTOM signals
are used by the Waveform Generator for handling the special cases of the extreme values in
some modes of operation (See Section “13.9” on page 123.)
A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (that
is, counter resolution). In addition to the counter resolution, the TOP value defines the period
time for waveforms generated by the Waveform Generator.
Figure 13-4 shows a block diagram of the Output Compare unit. The small “n” in the register and
bit names indicates the device number (n = n for Timer/Counter n), and the “x” indicates Output
Compare unit (A/B/C). The elements of the block diagram that are not directly a part of the Out-
put Compare unit are gray shaded.
Figure 13-4. Output Compare Unit, Block Diagram
The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation
(PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the
double buffering is disabled. The double buffering synchronizes the update of the OCRnx Com-
pare Register to either TOP or BOTTOM of the counting sequence. The synchronization
OCFnx (Int.Req.)
= (16-bit Comparator )
OCRnx Buffer (16-bit Register)
OCRnxH Buf. (8-bit)
OCnx
TEMP (8-bit)
DATA BUS (8-bit)
OCRnxL Buf. (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit)
TCNTnL (8-bit)
COMnx1:0
WGMn3:0
OCRnx (16-bit Register)
OCRnxH (8-bit)
OCRnxL (8-bit)
Waveform Generator
TOP
BOTTOM
相关PDF资料 |
PDF描述 |
|---|---|
| IS80C52CXXX-20:R | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQCC44 |
| IS80C52CXXX-25:D | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQCC44 |
| IS80C52CXXX-25:R | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQCC44 |
| IS80C52CXXX-25SHXXX:D | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQCC44 |
| IS80C52CXXX-30SHXXX:RD | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, PQCC44 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IS80C86 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| IS80C86-2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| IS80C86-2R2490 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| IS80C88 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| IS80C88-2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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