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参数资料
| 型号： | IS80C52CXXX-12:D |
| 厂商： | TEMIC SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44 |
| 文件页数： | 40/134页 |
| 文件大小： | 3805K |
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134
8011Q–AVR–02/2013
ATmega164P/324P/644P
Note:
1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the
WGMn2:0 definitions. However, the functionality and
location of these bits are compatible with previous versions of the timer.
13.11.2
TCCR1B – Timer/Counter1 Control Register B
Bit 7 – ICNCn: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is
activated, the input from the Input Capture pin (ICPn) is filtered. The filter function requires four
successive equal valued samples of the ICPn pin for changing its output. The Input Capture is
therefore delayed by four Oscillator cycles when the noise canceler is enabled.
Bit 6 – ICESn: Input Capture Edge Select
This bit selects which edge on the Input Capture pin (ICPn) that is used to trigger a capture
event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICESn bit is written to one, a rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICESn setting, the counter value is copied into the
Input Capture Register (ICRn). The event will also set the Input Capture Flag (ICFn), and this
can be used to cause an Input Capture Interrupt, if this interrupt is enabled.
Table 13-5.
Waveform Generation Mode Bit Description
Mode
WGMn3
WGMn2
(CTCn)
WGMn1
(PWMn1)
WGMn0
(PWMn0)
Timer/Counter Mode of
Operation
TOP
Update of
OCRn
x at
TOVn Flag
Set on
0
Normal
0xFFFF
Immediate
MAX
1
0
1
PWM, Phase Correct, 8-bit
0x00FF
TOP
BOTTOM
2
0
1
0
PWM, Phase Correct, 9-bit
0x01FF
TOP
BOTTOM
3
0
1
PWM, Phase Correct, 10-bit
0x03FF
TOP
BOTTOM
4
0
1
0
CTC
OCRnA
Immediate
MAX
5
0
1
0
1
Fast PWM, 8-bit
0x00FF
BOTTOM
TOP
6
0
1
0
Fast PWM, 9-bit
0x01FF
BOTTOM
TOP
7
0
1
Fast PWM, 10-bit
0x03FF
BOTTOM
TOP
8
100
0
PWM, Phase and Frequency
Correct
ICRn
BOTTOM
9
100
1
PWM, Phase and Frequency
Correct
OCRnA
BOTTOM
10
1
0
1
0
PWM, Phase Correct
ICRn
TOP
BOTTOM
11
1
0
1
PWM, Phase Correct
OCRnA
TOP
BOTTOM
12
1
0
CTC
ICRn
Immediate
MAX
13
1
0
1
(Reserved)
–
14
1
0
Fast PWM
ICRn
BOTTOM
TOP
15
1
Fast PWM
OCRnA
BOTTOM
TOP
Bit
765
4
3
2
1
0
ICNC1
ICES1
–
WGM13
WGM12
CS12
CS11
CS10
TCCR1B
Read/Write
R/W
R
R/W
Initial Value000
0
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