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参数资料
| 型号： | IS80C86 |
| 厂商： | INTERSIL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, 5 MHz, MICROPROCESSOR, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 19/36页 |
| 文件大小： | 693K |
| 代理商： | IS80C86 |
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166
FIGURE 8B. BUS TIMING - MAXIMUM MODE (USING 82C88)
NOTES:
18. Signals at 82C84A or 82C86 are shown for reference only.
19. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active
high 82C88 CEN.
20. Status inactive in state just prior to T4.
21. Cascade address is valid between first and second INTA cycles.
22. Two INTA cycles run back-to-back. The 80C86 local ADDR/DATA bus is floating during both INTA cycles. Control for pointer address is
shown for second INTA cycle.
Waveforms (Continued)
T1
T2
T3
T4
TW
TCLSH
(SEE NOTE 20))
TCLDX2
TCLDV
TCLAX
TCLMH
(18) TCLML
TCHDTH
(19) TCLMH
TCVNX
TCLAV
TCHSV
TCLSH
CLK
S2, S1, S0 (EXCEPT HALT)
WRITE CYCLE
AD15-AD0
DEN
AMWC OR AIOWC
MWTC OR IOWC
82C88
OUTPUTS
SEE NOTES
18, 19
INTA CYCLE
AD15-AD0
(SEE NOTES 21, 22)
AD15-AD0
MCE/PDEN
DT/R
INTA
DEN
82C88 OUTPUTS
SEE NOTES 18, 19
RESERVED FOR
CASCADE ADDR
(25) TCLAZ
(30) TCLMCH
TCVNV
SOFTWARE
HALT - RD, MRDC, IORC, MWTC, AMWC, IOWC, AIOWC, INTA, S0, S1 = VOH
(18) TCLML
TCLMH (19)
TCLDX1 (7)
(18)TCLML
POINTER
INVALID ADDRESS
AD15-AD0
S2
TCHDTL
TCHSV (21)
(34)
(22)
(33)
(24)
DATA
TCVNX (36)
(19)
(6)
TDVCL
TCLMCL
(32)
(41)
(42)
(35)
(36)
(23)
(21)
(22)
TCLAV
(23)
TCVNV
(35)
(28) TSVMCH
80C86
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