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参数资料
| 型号： | IS80C88-2 |
| 厂商： | INTERSIL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | CMOS 8/16-Bit Microprocessor |
| 中文描述： | 16-BIT, 8 MHz, MICROPROCESSOR, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 11/32页 |
| 文件大小： | 246K |
| 代理商： | IS80C88-2 |
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3-11
I/O Addressing
In the 80C88, I/O operations can address up to a maximum
of 64K I/O registers. The I/O address appears in the same
format as the memory address on bus lines A15-A0. The
address lines A19-A16 are zero in I/O operations. The vari-
able I/O instructions, which use register DX as a pointer,
have full address capability, while the direct I/O instructions
directly address one or two of the 256 I/O byte locations in
page 0 of the I/O address space. I/O ports are addressed in
the same manner as memory locations.
Designers familiar with the 8085 or upgrading an 8085
design should note that the 8085 addresses I/O with an 8-bit
address on both halves of the 16-bit address bus. The
80C88 uses a full 16-bit address on its lower 16 address
lines.
External Interface
Processor Reset and Initialization
Processor initialization or start up is accomplished with
activation (HIGH) of the RESET pin. The 80C88 RESET is
required to be HIGH for greater than four clock cycles. The
80C88 will terminate operations on the high-going edge of
RESET and will remain dormant as long as RESET is HIGH.
The low-going transition of RESET triggers an internal reset
sequence for approximately 7 clock cycles. After this interval
the 80C88 operates normally, beginning with the instruction
in absolute location FFFFOH (see Figure 2). The RESET
input is internally synchronized to the processor clock. At
initialization, the HIGH to LOW transition of RESET must
occur no sooner than 50
μ
s after power up, to allow complete
initialization of the 80C88.
NMI will not be recognized if asserted prior to the second
CLK cycle following the end of RESET.
Bus Hold Circuitry
To avoid high current conditions caused by floating inputs to
CMOS devices and to eliminate the need for pull-up/down
resistors, “bus-hold” circuitry has been used on 80C88 pins
2-16, 26-32 and 34-39 (see Figure 6A and 6B). These
circuits maintain a valid logic state if no driving source is
present (i.e., an unconnected pin or a driving source which
goes to a high impedance state).
To override the “bus hold” circuits, an external driver must be
capable of supplying 400
μ
A minimum sink or source current
at valid input voltage levels. Since this “bus hold” circuitry is
active and not a “resistive” type element, the associated
power supply current is negligible. Power dissipation is sig-
nificantly reduced when compared to the use of passive pull-
up resistors.
Interrupt Operations
Interrupt operations fall into two classes: software or
hardware initiated. The software initiated interrupts and
software aspects of hardware interrupts are specified in the
instruction set description. Hardware interrupts can be
classified as nonmaskable or maskable.
Interrupts result in a transfer of control to a new program
location. A 256 element table containing address pointers to
the interrupt service program locations resides in absolute
locations 0 through 3FFH (see Figure 2), which are reserved
for this purpose. Each element in the table is 4 bytes in size
and corresponds to an interrupt “type”. An interrupting
device supplies an 8-bit type number, during the interrupt
acknowledge sequence, which is used to vector through the
appropriate element to the new interrupt service program
location.
TABLE 7.
S2
S1
S0
CHARACTERISTICS
0
0
0
Interrupt Acknowledge
0
0
1
Read I/O
0
1
0
Write I/O
0
1
1
Halt
1
0
0
Instruction Fetch
1
0
1
Read Data from Memory
1
1
0
Write Data to Memory
1
1
1
Passive (No Bus Cycle)
TABLE 8.
S4
S3
CHARACTERISTICS
0
0
Alternate Data (Extra Segment)
0
1
Stack
1
0
Code or None
1
1
Data
FIGURE 19A. BUS HOLD CIRCUITRY PIN 2-16, 35-39
FIGURE 19B. BUS HOLD CIRCUITRY PIN 26-32, 34
OUTPUT
DRIVER
INPUT
BUFFER
INPUT
PROTECTION
CIRCUITRY
BOND
PAD
EXTERNAL
PIN
P
V
CC
OUTPUT
DRIVER
INPUT
BUFFER
INPUT
PROTECTION
CIRCUITRY
BOND
PAD
EXTERNAL
PIN
80C88
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