参数资料
型号: ISL12024IVZ
厂商: Intersil
文件页数: 10/25页
文件大小: 0K
描述: IC RTC/CALENDAR EEPROM 8-TSSOP
标准包装: 960
类型: 时钟/日历
特点: 警报器,闰年,唯一 ID
时间格式: HH:MM:SS(12/24 小时)
数据格式: YY-MM-DD-dd
接口: I²C,2 线串口
电源电压: 2.7 V ~ 5.5 V
电压 - 电源,电池: 1.8 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 8-TSSOP
包装: 管件
18
FN6370.3
August 18, 2008
Acknowledge Polling
Disabling of the inputs during non-volatile write cycles can
be used to take advantage of the 12ms (typ) write cycle time.
Once the stop condition is issued to indicate the end of the
master’s byte load operation, the ISL12024 initiates the
internal non-volatile write cycle. Acknowledge polling can
begin immediately. To do this, the master issues a start
condition followed by the Memory Array Slave Address Byte
for a write or read operation (AEh or AFh). If the ISL12024 is
still busy with the non-volatile write cycle, then no ACK will
be returned. When the ISL12024 has completed the write
operation, an ACK is returned and the host can proceed with
the read or write operation. See the flow chart in
Figure 20. Note: Do not use the CCR Slave byte (DEh or
DFh) for Acknowledge Polling.
Read Operations
There are three basic read operations: Current Address
Read, Random Read and Sequential Read.
Current Address Read
Internally the ISL12024 contains an address counter that
maintains the address of the last word read incremented by
one. Therefore, if the last read was to address n, the next
read operation would access data from address n+1. On
power-up, the 16-bit address is initialized to 00h. In this way,
a current address read immediately after the power-on reset
can download the entire contents of memory starting at the
first location. Upon receipt of the Slave Address Byte with
the R/W bit set to one, the ISL12024 issues an
acknowledge, then transmits 8 data bits. The master
terminates the read operation by not responding with an
acknowledge during the ninth clock and issuing a stop
condition. See Figure 19 for the address, acknowledge, and
data transfer sequence.
WORD
ADDRESS 0
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
WORD
ADDRESS 1
DATA
(n)
A
C
K
A
C
K
A
C
K
SDA BUS
SIGNALS FROM
THE SLAVE
SIGNALS FROM
THE MASTER
0
DATA
(1)
A
C
K
1
≤ n ≤ 16 for EEPROM ARRAY
1
≤ n ≤ 8 for CCR
1
0 0 00 00 0
FIGURE 18. PAGE WRITE SEQUENCE
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
DATA
A
C
K
SDA BUS
SIGNALS FROM
THE SLAVE
SIGNALS FROM
THE MASTER
1
FIGURE 19. CURRENT ADDRESS READ SEQUENCE
ACK
RETURNED?
ISSUE MEMORY ARRAY SLAVE
ADDRESS BYTE
AFH (READ) OR AEH (WRITE)
BYTE LOAD
COMPLETED BY
ISSUING STOP.
ENTER ACK POLLING
ISSUE STOP
ISSUE START
NO
YES
ISSUE STOP
NO
CONTINUE
NORMAL READ OR
WRITE COMMAND
SEQUENCE
PROCEED
YES
NON-VOLATILE WRITE
CYCLE COMPLETE. CONTINUE
COMMAND SEQUENCE?
FIGURE 20. ACKNOWLEDGE POLLING SEQUENCE
ISL12024
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