参数资料
型号: ISL12024IVZ
厂商: Intersil
文件页数: 15/25页
文件大小: 0K
描述: IC RTC/CALENDAR EEPROM 8-TSSOP
标准包装: 960
类型: 时钟/日历
特点: 警报器,闰年,唯一 ID
时间格式: HH:MM:SS(12/24 小时)
数据格式: YY-MM-DD-dd
接口: I²C,2 线串口
电源电压: 2.7 V ~ 5.5 V
电压 - 电源,电池: 1.8 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 8-TSSOP
包装: 管件
22
FN6370.3
August 18, 2008
Alarm Operation Examples
Below are examples of both Single Event and periodic
Interrupt Mode alarms.
EXAMPLE 1
Alarm0 set with single interrupt (IM = “0”)
A single alarm will occur on January 1 at 11:30am.
A. Set Alarm0 registers as follows:
B. Also, the AL0E bit must be set as follows:
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30am on January 1 (after
seconds changes from 59 to 00) by setting the AL0 bit in the
status register to “1” and also bringing the IRQ/FOUT output
low.
EXAMPLE 2
Pulsed interrupt once per minute (IM = “1”)
Interrupts at one minute intervals when the seconds register
is at 30 seconds.
A. Set Alarm0 registers as follows:
B. Set the Interrupt register as follows:
Once the registers are set, the following waveform will be
seen at IRQ/FOUT:
Note that the status register AL0 bit will be set each time the
alarm is triggered, but does not need to be read or cleared.
I2C Communications During Battery Backup
Operation in Battery Backup Mode is affected by the BSW
and SBIB bits as described earlier. These bits allow flexible
operation of the serial bus and EEPROM in Battery Backup
Mode, but certain operational details need to be clear before
utilizing the different modes. Table 8 describes four different
modes possible with using the BSW and SBIB bits, and how
they affect the serial interface and battery backup operation.
Mode A - In this mode, selection bits indicate a Standard
Mode switchover combined with I2C operation in Battery
Backup Mode. When the VDD voltage drops below the
lower of VTRIP or VBAT, then the device will enter Battery
Backup Mode. If the microcontroller and bus pull-ups are
also powered by the battery, then the ISL12024 can
communicate in Battery Backup Mode.
Mode B - In this mode selection, bits indicate Legacy
Mode switchover combined with I2C operation in Battery
Backup Mode. When the VDD voltage drops below VBAT,
the device will enter Battery Backup Mode. If the
microcontroller and bus pull-ups are also powered by the
battery, then the ISL12024 can communicate in Battery
Backup Mode. This mode places the ISL12024 device in
the same operating mode as the X1226 legacy device.
Mode C - This mode combines Standard Mode battery
switchover with no I2C operation in Battery Backup Mode.
When the VDD voltage drops below the lower of VTRIP or
ALARM0
REGISTER
BIT
DESCRIPTION
76
543210
HEX
SCA0
00
000000
00h
Seconds disabled
MNA0
10
110000
B0h Minutes set to 30,
enabled
HRA0
1
0
010001
91h
Hours set to 11,
enabled
DTA0
10
000001
81h
Date set to 1,
enabled
MOA0
10
000001
81h
Month set to 1,
enabled
DWA0
00
000000
00h
Day of week
disabled
CONTROL
REGISTER
BIT
DESCRIPTION
7654
3210
HEX
INT
0010
0000
x0hEnable Alarm
FIGURE 24. SUPER CAPACITOR CHARGING CIRCUIT
VDD
VBAT
VSS
SUPER CAP
2.7V TO 5.5V
ALARM0
REGISTER
BIT
DESCRIPTION
76543210 HEX
SCA0
10110000 B0h Seconds set to 30,
enabled
MNA0
00000000 00h Minutes disabled
HRA0
00000000 00h Hours disabled
DTA0
00000000 00h Date disabled
MOA0
00000000 00h Month disabled
DWA0
00000000 00h Day of week disabled
CONTROL
REGISTER
BIT
DESCRIPTION
76543210 HEX
INT
10100000
x0hEnable Alarm and Int
Mode
60s
RTC AND ALARM REGISTERS ARE BOTH 30s
ISL12024
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