参数资料
型号: ISL1801IVZ
厂商: Intersil
文件页数: 18/29页
文件大小: 0K
描述: IC CONV SOLAR PWR 48TSSOP
标准包装: 390
应用: 转换器,太阳能
输入电压: 9 V ~ 90 V
输出数: 4
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-TFSOP(0.240",6.10mm 宽)
供应商设备封装: 48-TSSOP
包装: 管件
ISL1801
ISL1801
120μA
LATCHRP
T
One-
shot
FF2
Q
Q
SET
CLR
S
R
OCSET
R1
C1
RPWM3
CMP1O
CMP2O
S
R
SET
CLR
Q
Q
FF1
S3
PGND3
PHASE3
I1
PWM3
PVCC3
POR
FIGURE 18. LOW-SIDE DRIVER LOGIC
DRIVE3
PGND3
Q1
Once the overcurrent protection is triggered flip-flop FF2 is set
forcing DRIVE3 low. RPWM3 or PWM3 must be pulled low to
reset an OCP event. Since the set input of flip-flop FF2 overrides
the reset input, DRIVE3 is always held low in an overcurrent
condition even if RWPM3 = 0.
The OCP flip-flop output also triggers a one-shot block to
generate a narrow pulse setting LATCHRPT low for 1μs.
For normal operation an OCP event terminates the DRIVE3 on state
early by forcing DRIVE3 to PGND3. The OCP event is reset by setting
PWM3 = 0. This allows DRIVE3 to be turned on by the following
Dual High Speed Comparator
ISL1801 has two high speed comparators for fault detection. The
output of either comparator can set the flip-flop FF1 to indicate a
fault at the open-drain LATCHRPT pin. The fault can be cleared by
setting RPWM3 = 0 to reset flip-flop FF1.
The two comparators are identical but only the output of
comparator 1 (CMP1) is available at the CMP1O pin. CMP1O is a
push-pull output and its output high level is clamped to VDDREF.
The fault detection logic is shown in Figure 20.
PWM3 = 1 pulse. However, special attention is needed for long-term
or continuous OCP operation. If the OCP is continuously triggered
with RPWM3 = 0 and PWM3 = 1, then a very high switching
frequency may occur on the DRIVE3 pin. Referring to Figure 18 the
following sequence of events will lead to this oscillation. When I1 is
CMP2+
CMP2-
CMP1+
CMP2
VDDREF
OCP3
S
R
SET
CLR
Q
Q
ONE
SHOT
FF1
LATCHRPT
larger than the preset OCP level, it may trigger OCP immediately
when DRIVE3 = 1. Once OCP is triggered, DRIVE3 is pulled low, and
S3 is turned off setting the OCP comparator output low. Since
RPWM3 = 0, the flip-flop FF2 is reset immediately. However, the 1μs
CMP1-
CMP1O
RPWM3
CMP1
ISL1801
one-shot will keep LATCHRPT low for at least 1μs forcing the DRIVE3
pin low for at least 1μs. After 1μs DRIVE3 is forced high resulting in
another OCP. This operation repeats until PWM3 = 0, RPWM3 = 1 or
I1 drops below the OCP threshold. This condition may result in a
100kHz switching frequency at DRIVE3.
BDRIVE CONTROL LOGIC
The BDRIVE pin is controlled by the BCMD signal. When
BCMD = 1, the BDRIVE output is connected to PVCC3 by its upper
switch. When BCMD = 0 the BDRIVE pin is connected to PGND4
through its lower switch.
When any fault condition occurs the LATCHRPT signal is set low.
It will also set flip-flop FF3 and connect the BDRIVE pin to PGND4
until flip-flop FF3 is reset by setting BRESET = 1. BDRIVE is held
at PGND4 prior to POR. The BDRIVE logic is shown in Figure 19.
FIGURE 20. FAULT DETECTION LOGIC
Precision Amplifier
The ISL1801 includes a precision amplifier for current sensing.
This low offset and low temperature drift OPAMP can be used to
accurately amplify the voltage drop across a known shunt
resistor to provide a current measurement for the MCU. Due to
the very low amplitude input signal, it is necessary to include
some capacitance as a noise filter. The typical application circuit
is shown in Figure 21. The current sense gain is set by the ratio of
R1/R2. Capacitor C1 implements a low-pass filter to reduce high
frequency noise effectively averaging the desired signal. C2 is
optional and can provide additional noise filtering if required.
C1
R1
AMP-
R2
LATCHRPT
BRESET
BCMD
S
R
SET
CLR
Q
Q
FF3
PVCC3
BRIVE
Q2
AMPO
VDDREF
AMP+
C2
R2
Rs
-
+
I SENSE
PGND4
POR
C1
R1
PGND
FIGURE 19. BDRIVE CONTROL LOGIC
18
FIGURE 21. PRECISION CURRENT SENSE AMPLIFIER
FN8259.0
June 29, 2012
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