参数资料
型号: ISL1801IVZ
厂商: Intersil
文件页数: 4/29页
文件大小: 0K
描述: IC CONV SOLAR PWR 48TSSOP
标准包装: 390
应用: 转换器,太阳能
输入电压: 9 V ~ 90 V
输出数: 4
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-TFSOP(0.240",6.10mm 宽)
供应商设备封装: 48-TSSOP
包装: 管件
ISL1801
Pin Descriptions (Continued)
TSSOP
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
SYMBOL
RPWM3
BCMD
BRESET
WDI
VDDREF
LATCHRPT
PGOOD2
AMPO
AMP-
AMP+
SGND
CMP1+
CMP1-
CMP1O
CMP2-
CMP2+
FB2
TON2
PGND2
PHASE2
BOOT2
VIN2
VCC5V
GND
PRELOAD
FB1
TON1
TIMER
DESCRIPTION
The reset signal for both flip-flops in the LATCHRPT circuit and overcurrent-protection circuit of DRIVE3/PHASE3. RPWM3=0
will reset both flip-flops. Avoid running PWM3=1 with RPWM3=0 for a long time or at very high frequency, since it may result
in very high switching frequency at DRIVE3 in the overcurrent protection condition.
Logic input to control BDRIVE.
Logic input to reset the LATCHRPT flip-flop in the BDRIVE control circuit.
Watch-dog circuit clock input signal.
Reference signal for output signals to the MCU. Connect this pin to V OUT2 , which provides a clamp voltage for all the output
pins (CMP1O, AMPO) interfacing with the MCU.
Open drain output signal. When either comparator or Phase3 overcurrent protection is triggered, this pin is pulled LOW to
inform the MCU. The two internal flip-flops used to latch these faults can be reset by setting RWPM3=0.
Open drain output pin indicating power good for the low voltage regulator. A logic low signal at the watch-dog output will also
pull this pin LOW allowing it to reset the MCU in either fault condition.
Integrated amplifier output.
Integrated amplifier inverting input.
Integrated amplifier non-inverting input.
The ground pin of the sensitive control circuits biased by VCC5V. Connect this pin to a ground plane with minimum noise.
Comparator 1 non-inverting input.
Comparator 1 inverting input.
Comparator 1 output. This signal also triggers the flip-flop for the LATCHRPT signal.
Comparator 2 inverting input.
Comparator 2 non-inverting input.
The feedback sense pin for the low voltage switching regulator. The output voltage is programmable by a resistor divider
feeding back the output voltage.
On-time adjustment for the secondary (low voltage) switching regulator. Connect a resistor from this pin to the input voltage
of the low voltage regulator to adjust the ON-time and switching frequency.
The ground pin of the low voltage switching regulator’s power stage. There are switching power current pulses coming out of
this pin. Place the ground pad of the input power stage decoupling cap as close to this pin as possible.
The phase node of the low voltage switching regulator. This pin should be connected to the output inductor.
The boot pin of the low voltage switching regulator. An external bootstrap capacitor is required. This pin provides bias voltage
to the high-side MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive the internal N-channel MOSFET.
The boot diode is included within the IC.
Input of the low voltage switching regulator. This pin is connected to the drain of the internal high side MOSFET.
The output of the internal 5V LDO providing the bias supply for the IC. A 1μF ceramic decoupling capacitor should be placed
from this pin to ground.
The analog ground pin.
Place a resistor from this pin to V OUT1 to provide the loading for the high voltage switching regulator. When this load can be
successfully driven the low voltage switching regulator will be enabled. If the PV module output power is insufficient, the low
voltage switching regulator will not start.
The feedback sense pin for the high voltage switching regulator. The output voltage is programmable by a resistor divider
feeding back the output voltage.
On-time adjustment for the high voltage switching regulator. Connect a resistor from this pin to the input voltage of the high
voltage regulator to adjust the ON-time and switching frequency.
Tie a resistor from VCC5V to this pin and a cap from this pin to ground. The RC time constant sets the time needed for both
start-up and watch-dog timing. A minimum of 0.01μF should be connected to this pin to filter the switching noise from BOOT1.
The pull-up resistor should not be more than 200k ? to assure correct operation.
4
FN8259.0
June 29, 2012
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