参数资料
型号: ISL33001IUZ
厂商: Intersil
文件页数: 11/18页
文件大小: 0K
描述: IC BUS BUFF HOTSWAP 2WR 8MSOP
标准包装: 50
类型: 缓冲器
Tx/Rx类型: I²C Logic
电容 - 输入: 10pF
电源电压: 2.3 V ~ 5.5 V
电流 - 电源: 4mA
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: 8-MSOP
包装: 管件
配用: ISL33001MSOPEVAL1Z-ND - EVAL BOARD ISL33001 8MSOP
ISL33001, ISL33002, ISL33003
2
FN7560.5
December 19, 2013
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL33001IRTZ
3001
-40 to +85
8 Ld TDFN (0.65mm Pitch)
L8.3x3A
ISL33001IRT2Z
01R2
-40 to +85
8 Ld TDFN (0.5mm Pitch)
L8.3x3H
ISL33001IBZ
33001 IBZ
-40 to +85
8 Ld SOIC
M8.15
ISL33001IUZ
33001
-40 to +85
8 Ld MSOP
M8.118
ISL33002IRTZ
3002
-40 to +85
8 Ld TDFN (0.65mm Pitch)
L8.3x3A
ISL33002IRT2Z
02R2
-40 to +85
8 Ld TDFN (0.5mm Pitch)
L8.3x3H
ISL33002IUZ
33002
-40 to +85
8 Ld MSOP
M8.118
ISL33003IRTZ
3003
-40 to +85
8 Ld TDFN (0.65mm Pitch)
L8.3x3A
ISL33003IRT2Z
03R2
-40 to +85
8 Ld TDFN (0.5mm Pitch)
L8.3x3H
ISL33003IUZ
33003
-40 to +85
8 Ld MSOP
M8.118
ISL33001MSOPEVAL1Z
ISL33001 Evaluation Board
ISL33002MSOPEVAL1Z
ISL33002 Evaluation Board
ISL33003MSOPEVAL1Z
ISL33003 Evaluation Board
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL33001, ISL33002, ISL33003. For more information on MSL please
see techbrief TB363.
Pin Configurations
ISL33001
(8 LD TDFN)
TOP VIEW
ISL33001
(8 LD SOIC, MSOP)
TOP VIEW
ISL33002
(8 LD TDFN)
TOP VIEW
ISL33002
(8 LD MSOP)
TOP VIEW
3
2
1
SCL_IN
GND 4
6
7
8
5
EN
VCC1
READY
SCL_OUT
SDA_IN
SDA_OUT
PAD
6
7
8
5
3
2
1
4
GND
VCC1
EN
READY
SDA_IN
SDA_OUT
SCL_IN
SCL_OUT
3
2
1
GND 4
6
7
8
5
VCC1
ACC
PAD
VCC2
SCL_IN
SCL_OUT
SDA_IN
SDA_OUT
6
7
8
5
3
2
1
4
VCC2
GND
VCC1
ACC
SDA_IN
SDA_OUT
SCL_IN
SCL_OUT
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