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参数资料
| 型号： | ISL33001IUZ |
| 厂商： | Intersil |
| 文件页数： | 18/18页 |
| 文件大小： | 0K |
| 描述： | IC BUS BUFF HOTSWAP 2WR 8MSOP |
| 标准包装： | 50 |
| 类型： | 缓冲器 |
| Tx/Rx类型： | I²C Logic |
| 电容 - 输入： | 10pF |
| 电源电压： | 2.3 V ~ 5.5 V |
| 电流 - 电源： | 4mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-MSOP |
| 包装： | 管件 |
| 配用： | ISL33001MSOPEVAL1Z-ND - EVAL BOARD ISL33001 8MSOP |
ISL33001, ISL33002, ISL33003
9
FN7560.5
December 19, 2013
Coming out of UVLO but prior to a valid connection state, the SDA
and SCL pins are pre-charged to 1V to allow hot insertion.
Because the bus at any time can be between 0V and VCC,
pre-charging the I/O pins to 1V reduces the maximum
differential voltage from the buffer I/O pin and the active bus.
The pre-charge circuitry reduces system disturbance when the IC
is hot plugged into a live back plane that may have the bus
communicating with other devices.
Note - For ISL33001 and ISL33003 with EN pins, the pre-charge
circuitry is active only after coming out of UVLO and having the
device enabled.
Connection Circuitry
Once a valid connection condition is met, the buffer is active and
the input stage of the SDA/SCL pins is controlled by external
drivers. The output of the buffer will follow the input of the buffer.
The directionality of the IN/OUT pins are not exclusive
(bi-directional operation) and functionally behave identical to
each other. Being a two channel buffer, the SDA and SCL pins
also behave identically. In addition, the SDA and SCL portions of
the buffer are independent from each other. The SDA pins can be
driven in one direction while the SCL pins can be driven opposite.
Refer to Figure 10 for the operation of the bi-directional buffer.
When the input stage of the buffer on one side is driven low by an
external device, the output of the buffer drives an open-drain
transistor to pull the ‘output’ pin low. The ‘output’ pin will
continue to be held low by the transistor until the external driver
on the ‘input’ releases the bus.
To prevent the buffer from entering a latched condition where
both internal transistors are actively pulling the I/O pins low, the
buffer is designed to be active in only one direction. The buffer
logic circuitry senses which input stage is being externally driven
low and sets that buffer to be the active one. For example,
referring to Figure 10, if SDA_OUT is externally driven low, buffer
U2 will be active and buffer U1 is inactive. M1 is turned on to
drive SDA_IN low, effectively buffering the signal from SDA_OUT
to SDA_IN. The low signal at the input of U1 will not turn M2 on
because U1 remains inactive, preventing a latch condition.
Buffer Output Low and Offset Voltage
By design, when a logic input low voltage is forced on the input of
the buffer, the output of the buffer will have an input to output
offset voltage. The output voltage of the buffer is determined by
Equation 1:
Where VOS is the buffer internal offset voltage, RPull-Up is the pull
up resistance on the SDA/SCL pin to VCC and RON is the ON
resistance of the buffer’s internal NMOS pull-down device. The
last term of the equation is the additional voltage drop developed
by sink current and the internal resistance of the transistor. The
typically 40mV. Reducing the pull-up resistor values increases
the sink current and increases the output voltage of the buffer for
Rise Time Accelerators
The ISL33001, ISL33002, ISL33003 buffer rise time
accelerators on the SDA/SCL pins improve the transient
performance of the system. Heavy load capacitance or weak
pull-up resistors on an Open-Drain bus cause the rise time to be
excessively long, which leads to data errors or reduced data rate
performance. The rise time accelerators are only active on the
low to high transitions and provide an active constant current
source to slew the voltage on the pin quickly (Figure 21).
The rise time accelerators are triggered immediately after the
buffer release threshold (approximately 30% of VCC) on both
sides of the buffer is crossed. Once triggered, the accelerators
are active for a defined pulse width (Figure 22) with the current
source turning off as it approaches the supply voltage.
Enable Pin (ISL33001 and ISL33003)
When driven high, the enable pin puts the buffer into its normal
operating state. After power-up, EN high will activate the bus
pre-charge circuitry and wait for a valid connection state to
enable the buffer and the accelerator circuitry.
Driving the EN pin low disables the accelerators, disables the
buffer so that signals on one side of the buffer will be isolated
from the other side, disables the pre-charge circuit and places
the device in a low power shutdown state.
READY Logic Pin (ISL33001 Only)
The READY pin is a digital output flag for signaling the status of
the buffer. The pin is the drain of an Open-Drain NMOS. Connect
a resistor from the READY pin to VCC1 to provide the high pull-up.
The recommended value is 10k.
When the buffer is disabled by having the EN pin low or if the
start-up sequencing is not complete, the READY pin will be pulled
low by the NMOS. When the buffer has the EN pin high and a
valid connection state is made at the SDA/SCL pins, the READY
pin will be pulled high by the pull-up resistor. The READY pin is
capable of sinking 3mA when pulled low while maintaining a
voltage of less than 0.4V.
ACC Accelerator Pin (ISL33002 Only)
The ACC logic pin controls the rise time accelerator circuitry of
the buffer. When ACC is driven high, the accelerators are enabled
and will be triggered when crossing the buffer release threshold.
When ACC is driven low, the accelerators are disabled.
For lightly loaded buses, having the accelerators active may
cause ringing or noise on the rising edge transition. Disabling the
accelerators will have the buffers continue to perform level
shifting with the VCC1 and VCC2 supplies and provide
capacitance buffering.
Propagation Delays
On a low to high transition, the rising edge signal is determined
by the bus pull-up resistor, load capacitance, and the accelerator
current from the ISL33001, ISL33002, ISL33003 buffer. Prior to
the accelerators becoming active, the buffer is connected and
the output voltage will track the input of the buffer. When the
accelerators activate the buffer connection is released and the
signal on each side of the buffer rises independently. The
V
OUT
V
IN
V
OS
V
CC/RPULL-UP
R
ON
×
[]
++
=
(EQ. 1)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL33001IUZ-T | 功能描述:I2C 接口集成电路 W/ANNEAL VIS25 8INCH I2C BUFR IND(-40 RoHS:否 制造商:NXP Semiconductors 电源电压-最大:5.5 V 电源电压-最小:2.3 V 最大工作频率:400 KHz 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-16 |
| ISL33001MSOPEVAL1Z | 功能描述:EVAL BOARD ISL33001 8MSOP RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PCI Express® (PCIe) 主要目的:接口，收发器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要属性:- 次要属性:- 已供物品:板 |
| ISL33002 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:I2C Bus Buffer with Rise Time Accelerators and Hot Swap Capability |
| ISL33002IRT2Z | 功能描述:I2C 接口集成电路 VIS25 8 INCH I2C BUFFER 8LD IND RoHS:否 制造商:NXP Semiconductors 电源电压-最大:5.5 V 电源电压-最小:2.3 V 最大工作频率:400 KHz 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-16 |
| ISL33002IRT2Z-T | 功能描述:I2C 接口集成电路 VIS25 8 INCH I2C BUFFER 8LD IND RoHS:否 制造商:NXP Semiconductors 电源电压-最大:5.5 V 电源电压-最小:2.3 V 最大工作频率:400 KHz 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-16 |
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