参数资料
| 型号： | ISL5585GCR-TK |
| 厂商： | Intersil |
| 文件页数： | 9/24页 |
| 文件大小： | 0K |
| 描述： | IC SLIC RINGING 3.3V VOB 32-QFN |
| 标准包装： | 1,000 |
| 功能： | 用户线路接口概念（SLIC） |
| 电路数： | 1 |
| 电源电压： | 3.3V |
| 功率（瓦特）： | 305mW |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（7x7） |
| 包装： | 带卷 (TR) |
| 包括： | 均衡和不均衡振铃，振铃声信号发生器，热关机，带警报指示器 |
17
If the loop length is greater than RKNEE , the device is
operating in the constant voltage, resistive feed region. The
power dissipated in this region is calculated using Equation 53.
Since the current relationships are different for constant
current versus constant voltage, the region of device
operation is critical to valid power dissipation calculations.
Reverse Active
Overview
The reverse active mode (RA, 011) provides the same
functionality as the forward active mode. On hook
transmission, DC loop feed and voice transmission are
supported. Loop supervision is provided by either the switch
hook detector (E0 = 1) or the ground key detector (E0 = 0).
The device may be operated from either high or low battery.
During reverse active the Tip and Ring DC voltage
characteristics exchange roles. That is, Ring is typically 4V
below ground and Tip is typically 4V more positive than
battery. Otherwise, all feed and voice transmission
characteristics are identical to forward active.
Silent Polarity Reversal
Changing from forward active to reverse active or vice versa
is referred to as polarity reversal. Many applications require
slew rate control of the polarity reversal event. Requirements
range from minimizing cross talk to protocol signalling.
The device uses an external low voltage capacitor, CPOL, to
set the reversal time. Once programmed, the reversal time
will remain nearly constant over various load conditions. In
addition, the reversal timing capacitor is isolated from the AC
loop, therefore loop stability is not impacted.
The internal circuitry used to set the polarity reversal time is
shown in Figure 11.
During forward active, the current from source I1 charges the
external timing capacitor CPOL and the switch is open. The
internal resistor provides a clamping function for voltages on
the POL node. During reverse active, the switch closes and
I2 (roughly twice I1) pulls current from I1 and the timing
capacitor. The current at the POL node provides the drive to
a differential pair which controls the reversal time of the Tip
and Ring DC voltages.
Where
time is the required reversal time. Polarized
capacitors may be used for CPOL. The low voltage at the
POL pin and minimal voltage excursion
±0.75V, are well
suited to polarized capacitors.
Power Dissipation
The power dissipation equations for forward active operation
also apply to the reverse active mode.
Ringing
Overview
The ringing mode (RNG, 100) provides linear amplification to
support a variety of ringing waveforms. A programmable ring
trip function provides loop supervision and auto disconnect
upon ring trip. The device is designed to operate from the
high battery during this mode.
Architecture
The device provides linear amplification to the signal applied
to the ringing input, VRS. The differential ringing gain of the
device is 80V/V. The circuit model for the ringing path is
shown in Figure 12.
The voltage gain from the VRS input to the Tip output is
40V/V. The resistor ratio provides a gain of 8 and the current
mirror provides a gain of 5. The voltage gain from the VRS
input to the Ring output is -40V/V.
The equations for the Tip and Ring outputs during ringing
are provided below.
P
FA IB
()
P
FA Q
()
V
BLxIB
()
R
LOOPxI
2
B
()
–
+
=
(EQ. 53)
FIGURE 11. REVERSAL TIMING CONTROL
CPOL
POL
I1
75k
I2
C
POL
time
75000
----------------
=
(EQ. 54)
FIGURE 12. LINEAR RINGING MODEL
TIP
RING
VRS
R/8
R
+
-
+
-
5:1
20
+
-
+
-
600K
VBH
2
V
T
V
BH
2
-----------
40
VRS
×
()
+
=
(EQ. 55)
V
R
V
BH
2
-----------
40
VRS
×
()
–
=
(EQ. 56
ISL5585
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