参数资料
型号: ISL6115AEVAL1Z
厂商: Intersil
文件页数: 9/10页
文件大小: 0K
描述: EVAL BOARD 1 FOR ISL6115A
标准包装: 1
系列: *
ISL6115A
ISL6115AEVAL1Z Board
The ISL6115AEVAL1Z is default provided as a +12V
high side switch controller with the CR level set at
~2.5A. See Figure 11 for ISL6115AEVAL1Z schematic
and Table 3 for BOM. Bias and load connection points
are provided along with test points for each IC pin.
With J1 installed the ISL6115A will be biased from the
+12V supply (V IN ) being switched. Connect the load to
VLOAD+. PWRON pin pulls high internally enabling the
ISL6115A if not driven low via PWRON test point or J2.
With R 3 = 1.24k Ω the CR Vth is set to 24.8mV and
with the 10m Ω sense resistor (R 1 ) the
ISL6115AEVAL1Z has a nominal CR level of 2.5~A. The
0.01μF delay time to latch-off capacitor results in a
nominal 1ms before latch-off of output after an OC
event.
Reconfiguring the ISL6115AEVAL1Z board for a higher
CR level can be done by changing the R SENSE and/or
R ISET resistor values as the provided FET is rated for a
much higher current.
VLOAD+
AGND
VOUT
R3
1
8
J2
PWRON
R1
Q1
R2
2
3
4
ISL6115A
U1
C2
7
6
5
R4
PGOOD
C TIM
C3
C1
VIN
J1
+12V
V BIAS
V BIAS
FIGURE 14. ISL6115AEVAL1Z HIGH SIDE SWITCH APPLICATION and PHOTOGRAPH
TABLE 3. BILL OF MATERIALS, ISL6115AEVAL1Z
COMPONENT
DESIGNATOR
U1
Q1
R1
R2
R3
R4
C1
C2
C3
J1
J2
COMPONENT NAME
ISL6115A
N-FET
Load Current Sense Resistor
Gate Stability Resistor
Overcurrent Voltage Threshold Set
Resistor
PGOOD Pull up Resistor
Gate Timing Capacitor
IC Decoupling Capacitor
Time Delay Set Capacitor
Bias Voltage Selection Jumper
PWRON Disable
9
COMPONENT DESCRIPTION
Intersil
11.5m Ω , 30V, 11.5A Logic Level N-Channel Power MOSFET or equivalent
WSL-2512 10m Ω 1W Metal Strip Resistor
20 Ω 0603 Chip Resistor
1.24k Ω 0603 Chip Resistor (Vth = 24.8mV)
10k Ω 0603 Chip Resistor
0.001μF 0402 Chip Capacitor (<2ms)
0.1μF 0402 Chip Capacitor
0.01μF 0402 Chip Capacitor (1ms)
Install if switched rail voltage is = +12V. Remove and provide separate
+12V bias voltage to U2 via V BIAS if ISL6116, ISL6117 or ISL6120 is
being evaluated.
Install J2 to disable U2. Connects PWRON to GND.
FN6855.1
April 23, 2010
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