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参数资料
| 型号： | ISL6142CB-T |
| 厂商： | Intersil |
| 文件页数： | 15/23页 |
| 文件大小： | 0K |
| 描述： | IC CONTROLLER HOT PLUG 14-SOIC |
| 标准包装： | 2,500 |
| 类型： | 热交换控制器 |
| 应用： | 通用型 VoIP |
| 内部开关： | 无 |
| 电源电压： | 36 V ~ 72 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 14-SOICN |
| 包装： | 带卷 (TR) |
ISL6142, ISL6152
The values of R4 = 549k, R5 = 6.49k, and R6 = 10k shown in
Figure 29 set the Under-Voltage threshold at 43V, and the
Over-Voltage, turn off threshold to 71V. The Under-Voltage
(UV) comparator has a hysteresis of 135mV’s (4.6V of
hysteresis on the supply) which correlates to a 38.4V turn off
voltage. The Over-Voltage comparator has a 25mV
hysteresis (1.4V of hysteresis on the supply) which
R1 resistor, and the V EE and SENSE pins should be direct
and as short as possible with zero current in the sense lines.
Note that in Figure 30 the traces from each side of the R1
resistor also connect to the R8 (IS+), and R7 (IS-) current
sensing resistors.
translates to a turn on voltage (supply decreasing) of
approximately 69.6V.
Q1 - is the FET that connects the input supply voltage to the
output load, when properly enabled. It needs to be selected
based on several criteria:
? Maximum voltage expected on the input supply (including
transients) as well as transients on the output side.
? Maximum current and power dissipation expected during
normal operation, usually at a level just below the current
limit threshold.
? Power dissipation and/or safe-operating-area
CORRECT
To V EE
and R7
To SENSE
and R8
INCORRECT
CURRENT
SENSE RESISTOR
I OC = --------------------
R sense
I inrush = I PU × -------
C L
C
considerations during current limiting and single retry
events.
? Other considerations include the GATE voltage threshold
which affects the r DS(ON) (which in turn, affects the
voltage drop across the FET during normal operation),
and the maximum gate voltage allowed (the IC’s GATE
output is clamped to ~14V).
R1 - is the Over-Current sense resistor also referred to as
R SENSE . If the input current is high enough, such that the
voltage drop across R1 exceeds the SENSE comparator trip
point (50mV nominal), the GATE pin will be pulled lower (to
~4V) and current will be regulated to 50mV/Rsense for the
programmed time-out period which is set by C3. The
Over-Current threshold is defined in Equation 3 below. If the
time-out period is exceeded the Over-Current latch will be
set and the FET will be turned off to protect the load from
excessive current. A typical value for R1 is 0.02 ? , which sets
an Over-Current trip point of; I OC = V/R = 0.05/0.02 = 2.5
Amps. To select the appropriate value for R1, the user must
first determine at what level of current it should trip, take into
account worst case variations for the trip point (50mV
± 10mV = ± 20%), and the tolerances of the resistor (typically
1% or 5%). Note that the Over-Current threshold should be
set above the inrush current level plus the expected load
current to avoid activating the current limit and time-out
circuitry during start-up. If the power good output
(PWRGD/PWRGD) is used to enable an external module,
the desired inrush current only needs to be considered. One
rule of thumb is to set the Over-Current threshold 2-3 times
higher than the normal operating current.
50mv
(EQ. 3)
The physical layout of the R1 sense resistor is critical to
avoid the possibility of false over current events. Since it is in
the main input-to-output path, the traces should be wide
enough to support both the normal current, and currents up
to the over-current trip point. The trace routing between the
15
FIGURE 30. SENSE RESISTOR LAYOUT GUIDELINES
CL - is the sum of all load capacitances, including the load’s
input capacitance itself. Its value is usually determined by
the needs of the load circuitry, and not the hot plug (although
there can be interaction). For example, if the load is a
regulator, then the capacitance may be chosen based on the
input requirements of that circuit (holding regulation under
current spikes or loading, filtering noise, etc.) The value
chosen will affect the peak inrush current. Note that in the
case of a regulator, there may be capacitors on the output of
that circuit as well; these need to be added into the
capacitance calculation during inrush (unless the regulator is
delayed from operation by the PWRGD/PWRGD signal).
RL - is the equivalent resistive value of the load and
determines the normal operating current delivered through the
FET. It also affects some dynamic conditions (such as the
discharge time of the load capacitors during a power-down).
A typical value might be 48 ? (I = V/R = 48/48 = A).
R2, C1, R3, C2 - are related to the GATE driver, as it
controls the inrush current.
R2 prevents high frequency oscillations; 10 ? is a typical
value. R2 = 10 ? .
R3 and C2 act as a feedback network to control the inrush
current as shown in Equation 4, where CL is the load
capacitance (including module input capacitance), and I PU is
the GATE pin charging current, nominally 50μA.
(EQ. 4)
2
Begin by choosing a value of acceptable inrush current for
the system, and then solve for C2.
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| ISL6142IB | 功能描述:IC CTRLR HOT PLUG NEG 14-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:100 系列:- 类型:热插拔开关 应用:通用 内部开关:是 电流限制:可调 电源电压:9 V ~ 13.2 V 工作温度:-40°C ~ 150°C 安装类型:表面贴装 封装/外壳:10-WFDFN 裸露焊盘 供应商设备封装:10-TDFN-EP（3x3） 包装:管件 |
| ISL6142IB-T | 功能描述:IC CTRLR HOT PLUG NEG 14-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:100 系列:- 类型:热插拔开关 应用:通用 内部开关:是 电流限制:可调 电源电压:9 V ~ 13.2 V 工作温度:-40°C ~ 150°C 安装类型:表面贴装 封装/外壳:10-WFDFN 裸露焊盘 供应商设备封装:10-TDFN-EP（3x3） 包装:管件 |
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