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参数资料
| 型号： | ISL6218CVZ-T |
| 厂商： | Intersil |
| 文件页数： | 11/19页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR INTEL PENT M 38-TSSOP |
| 标准包装： | 2,500 |
| 应用： | 处理器 |
| 电流 - 电源： | 1.4mA |
| 电源电压： | 4.75 V ~ 5.25 V |
| 工作温度： | -10°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 38-TSSOP |
| 包装： | 带卷 (TR) |
ISL6218
VID[0..5]
V CC_CORE
PGOOD
CURRENT VID CODE
<600ns
CURRENT VOLTAGE LEVEL
HIGH
NEW VID CODE
NEW VOLTAGE LEVEL
FIGURE 5. PLOT SHOWING TIMING OF VID CODE CHANGES AND CORE VOLTAGE SLEWING AS WELL AS PGOOD MASKING
VID[0..5]
VID CODE REMAINS THE SAME
STP_CPU
(DSEN)
VID COMMAND VOLTAGE
<3μs
V CC_CORE
V DEEP SLEEP
FIGURE 6. CORE VOLTAGE SLEWING TO 98.8% OF PROGRAMMED VID VOLTAGE FOR A LOGIC LEVEL LOW ON DSEN
VID[0..5]
VID CODE REMAINS THE SAME
STP_CPU
(DSEN)
DEEPER SLEEP
DPRSLPVR
(DRSEN)
V CC_CORE
V DEEP
SHORT DPRSLP CAUSES V CC_CORE TO RAMP-UP
V DEEPER
FIGURE 7. VCORE RESPONSE FOR DEEPER SLEEP COMMAND
Deep Sleep Enable (DSEN) and Deeper Sleep
Enable (DRSEN)
Table 2 shows logic states controlling modes of operation
Figure 6 and Figure 5 show the timing for transitions entering
and exiting Deep Sleep Mode and Deeper Sleep Mode,
controlled by the system signals STPCPU and DPRSLPVR.
Pins DSEN (Deep Sleep Enable) and DRSEN (Deeper
Sleep Enable) of the ISL6218 are connected to these 2
signals, respectively.
For the case when DSEN is logic high, and DRSEN is logic
low, the controller will operate in Active Mode and regulate
the output voltage to the VID commanded DAC voltage
minus the voltage “Droop” as determined by the load current.
Voltage “Droop” is the reduction of output voltage
proportional to output current.
11
When a logic low is seen on the DSEN and DRSEN is logic
low the controller will then regulate the output voltage to the
voltage seen on the DSV pin minus “Droop”.
When DSEN is logic low and DRSEN is logic high the
controller will operate in Deeper Sleep mode. The ISL6218
will then regulate to the voltage seen on the DRSV pin minus
“Droop”.
Deep and Deeper Sleep voltage levels are programmable
DISCONTINUOUS OPERATION - PSI
The ISL6218 Single-Phase PWM controller is a
Synchronous Buck Regulator. However, in Deep and Deeper
Sleep modes where the load current is low, the controller
operates as a standard buck regulator. This mode of
operation acts to eliminate negative inductor current by
truncating the low side MOSFET gate drive pulse, and
FN9101.6
August 6, 2007
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6218EVAL2 | 功能描述:EVALUATION BOARD 2 FOR ISL6218 RoHS:否 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:True Shutdown™ 主要目的:DC/DC，步升 输出及类型:1，非隔离 功率 - 输出:- 输出电压:- 电流 - 输出:1A 输入电压:2.5 V ~ 5.5 V 稳压器拓扑结构:升压 频率 - 开关:3MHz 板类型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
| ISL6219 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Microprocessor CORE Voltage Regulator Precision Multi-Phase BUCK PWM Controller for Mobile Applications |
| ISL6219 WAF | 制造商:Harris Corporation 功能描述: |
| ISL6219A | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Microprocessor CORE Voltage Regulator Precision Multi-Phase BUCK PWM Controller for Mobile Applications |
| ISL6219A_07 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Microprocessor CORE Voltage Regulator Precision Multi-Phase BUCK PWM Controller for Mobile Applications |
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