参数资料
型号: ISL6236AIRZ-T
厂商: Intersil
文件页数: 28/37页
文件大小: 0K
描述: IC MAIN PWR CTRLR QUAD 32-QFN
产品培训模块: Solutions for Industrial Control Applications
标准包装: 6,000
应用: 控制器,笔记本电脑电源系统
输入电压: 4.5 V ~ 25 V
输出数: 4
输出电压: 多重
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN 裸露焊盘(5x5)
包装: 带卷 (TR)
ISL6236A
40μs (MAX)
D2a. Finally, C 14 charges C 15 thru D2b when LGATE1
switched to high. CP output voltage is shown in Equation 4:
INDUCTOR
CURRENT
CP = V OUT1 + 2 ? V LGATE1 – 4 ? V D
where:
? V LGATE1 is the peak voltage of the LGATE1 driver
(EQ. 4)
Detection
FB<Reg.Point
ON-TIME (t ON ) ON)
Zero-Crossing
ZERO-CROSSING
DETECTION
0A
FB<REG.POINT
)
FIGURE 73. ULTRASONIC CURRENT WAVEFORMS
Reference and Linear Regulators (VREF3,
REF, LDO and 14V Charge Pump)
The 3.3V reference (VREF3) is accurate to ±1.5%
over-temperature, making VREF3 useful as a precision
system reference. VREF3 can supply up to 5mA for external
loads. Bypass VREF3 to GND with a 0.01μF capacitor.
Leave it open if there is no load.
The 2V reference (REF) is accurate to ±1% over- temperature,
also making REF useful as a precision system reference.
Bypass REF to GND with a 0.1μF (min) capacitor. REF can
supply up to 50μA for external loads.
An internal regulator produces a fixed 5V
(LDOREFIN < 0.2V) or 3.3V (LDOREFIN > VCC - 1V). In an
adjustable mode, the LDO output can be set from 0.7V to
4.5V. The LDO output voltage is equal to two times the
LDOREFIN voltage. The LDO regulator can supply up to
100mA for external loads. Bypass LDO with a minimum
4.7μF ceramic capacitor. When the LDOREFIN < 0.2V and
BYP voltage is 5V, the LDO bootstrap-switchover to an
internal 0.7 Ω P-Channel MOSFET switch connects BYP to
LDO pin while simultaneously shutting down the internal
linear regulator. These actions bootstrap the device,
powering the loads from the BYP input voltages, rather than
through internal linear regulators from the battery. Similarly,
when the BYP = 3.3V and LDOREFIN = VCC, the LDO
bootstrap-switchover to an internal 1.5 Ω P-Channel
? V D is the forward diode dropped across the Schottkys
SECFB is used to monitor the charge pump through the
resistive divider. In an event when SECFB dropped below
2V, the detection circuit force the highside MOSFET
(SMPS1) off and the lowside MOSFET (SMPS1) on for
300ns to allow CP to recharge and SECFB rise above 2V. In
the event of an overload on CP where SECFB cannot reach
more than 2V, the monitor will be deactivated. Special care
should be taken to ensure enough normal voltage ripple on
each cycle as to prevent CP shut-down. The SECFB pin has
~17mV of hysteresis, so the ripple should be enough to bring
the SECFB voltage above the threshold by ~3x the
hysteresis, or (2V + 3*17mV) = 2.051V. Reducing the CP
decoupling capacitor and placing a small ceramic capacitor
(10pF to 47pF) in parallel with the upper leg of the SECFB
resistor feedback network (R 1 of Figure 68), will also
increase the robustness of the charge pump.
Current-Limit Circuit (ILIM ) with r DS(ON)
Temperature Compensation
The current-limit circuit employs a "valley" current-sensing
algorithm. The ISL6236A uses the ON-resistance of the
synchronous rectifier as a current-sensing element. If the
magnitude of the current-sense signal at PHASE is above
the current-limit threshold, the PWM is not allowed to initiate
a new cycle. The actual peak current is greater than the
current-limit threshold by an amount equal to the inductor
ripple current. Therefore, the exact current-limit
characteristic and maximum load capability are a function of
the current-limit threshold, inductor value and input and
output voltage.
I PEAK
MOSFET switch connects BYP to LDO pin while
simultaneously shutting down the internal linear regulator.
No switchover action in adjustable mode.
I LOAD
Δ I
In Figure 68, the external 14V charge pump is driven by
LGATE1. When LGATE1 is low, D1a charged C 8 sourced
I LOAD(MAX)
I LIMIT
LOAD -
from OUT1. C 8 voltage is equal to OUT1 minus a diode
drop. When LGATE1 transitions to high, the charges from C 8
will transfer to C 12 through D1b and charge it to VLGATE1
plus VC8. As LGATE1 transitions low on the next cycle, C 12
I LIM ( VAL ) = I
TIME
Δ I
2
will charge C 14 to its voltage minus a diode drop through
FIGURE 74. “VALLEY” CURRENT LIMIT THRESHOLD POINT
28
FN6453.3
March 18, 2008
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