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参数资料
| 型号： | ISL62381CHRTZ |
| 厂商： | Intersil |
| 文件页数： | 20/23页 |
| 文件大小： | 0K |
| 描述： | IC PWR SUPPLY CONTROLLER 32TQFN |
| 标准包装： | 60 |
| 应用： | 电源控制器 |
| 输入电压： | 5.5 V ~ 25 V |
| 电源电压： | 5.5 V ~ 25 V |
| 电流 - 电源： | 150µA |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 供应商设备封装： | 32-TQFN（5x5） |
| 包装： | 管件 |
ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C
Where:
- I VALLEY is the difference of the DC component of the
inductor current minus 1/2 of the inductor ripple current
- I PEAK is the sum of the DC component of the inductor
current plus 1/2 of the inductor ripple current
- t ON is the time required to drive the device into
saturation
PIN 4 (VCC2)
ISL62381
AND ISL62382
PIN 21 (VIN)
Co
L2
L2 U2
Ci
- t OFF is the time required to drive the device into cut-off
Selecting The Bootstrap Capacitor
LINE OF SYMMETRY
Ci
The selection of the bootstrap capacitor is written as
Equation 27:
L1
U1
Δ V BOOT
Q g
C BOOT = ------------------------
Where:
(EQ. 27)
PGND PLANE
PHASE PLANES
VOUT PLANES
VIN PLANE
L1
Co
- Q g is the total gate charge required to turn on the
high-side MOSFET
- Δ V BOOT , is the maximum allowed voltage decay across
the boot capacitor each time the high-side MOSFET is
switched on
As an example, suppose the high-side MOSFET has a total
gate charge Q g , of 25nC at V GS = 5V, and a Δ V BOOT of
200mV. The calculated bootstrap capacitance is 0.125μF; for
a comfortable margin, select a capacitor that is double the
calculated capacitance. In this example, 0.22μF will suffice.
Use an X7R or X5R ceramic capacitor.
Layout Considerations
As a general rule, power should be on the bottom layer of
the PCB and weak analog or logic signals are on the top
layer of the PCB. The ground-plane layer should be adjacent
to the top layer to provide shielding. The ground plane layer
should have an island located under the IC, the
compensation components, and the FSET components. The
island should be connected to the rest of the ground plane
layer at one point.
FIGURE 30. SYMMETRIC LAYOUT GUIDE
Signal Ground and Power Ground
The bottom of these controllers TQFN package is the signal
ground (GND) terminal for analog and logic signals of the IC.
Connect the GND pad of these controllers to the island of
ground plane under the top layer using several vias for a
robust thermal and electrical conduction path. Connect the
input capacitors, the output capacitors, and the source of the
lower MOSFETs to the power ground (PGND) plane.
The following pin descriptions use ISL62381 as an example.
PGND (Pin 23)
This is the return path for the pull-down of the LGATE
low-side MOSFET gate driver. Ideally, PGND should be
connected to the source of the low-side MOSFET with a
low-resistance, low-inductance path.
VIN (Pin 21)
The VIN pin should be connected close to the drain of the
high-side MOSFET, using a low resistance and low
INDUCTOR
OUTPUT
CAPACITORS
SCHOTTKY
DIODE
LOW-SIDE
MOSFETS
VIAS TO
GROUND
PLANE
INDUCTOR
HIGH-SIDE
MOSFETS
GND
VOUT
PHASE
NODE
VIN
OUTPUT
CAPACITORS
SCHOTTKY
DIODE
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
inductance path.
VCC (Pins 4 and 5)
For best performance, place the decoupling capacitor very
close to the VCC and GND pins.
LDO5 (Pin 22)
For best performance, place the decoupling capacitor very
close to the LDO5 and respective PGND pin, preferably on
the same side of the PCB as the ISL62381 IC.
FIGURE 29. TYPICAL POWER COMPONENT PLACEMENT
EN (Pins 13 and 28) and PGOOD (Pins 1 and 8)
Because there are two SMPS outputs and only one PGND
pin, the power train of both channels should be laid out
symmetrically. The line of bilateral symmetry should be
drawn through pins 4 and 21 (pins 4 and 18 for ISL62383).
This layout approach ensures that the controller does not
favor one channel over another during critical switching
decisions. Figure 30 illustrates one example of how to
achieve proper bilateral symmetry.
20
These are logic signals that are referenced to the GND pin.
Treat as a typical logic signal.
OCSET (Pins 12 and 29) and ISEN (Pins 11 and 30)
For DCR current sensing, current-sense network, consisting
of R OCSET and C SEN , needs to be connected to the
inductor pads for accurate measurement. Connect R OCSET
to the phase-node side pad of the inductor, and connect
FN6665.5
May 13, 2011
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相关代理商/技术参数 |
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| ISL62381CHRTZ-T | 功能描述:IC PWR SUPPLY CONTROLLER 32TQFN RoHS:是 类别:集成电路 (IC) >> PMIC - 电源控制器，监视器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 应用:多相控制器 输入电压:- 电源电压:9 V ~ 14 V 电流 - 电源:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:40-WFQFN 裸露焊盘 供应商设备封装:40-TQFN-EP（5x5） 包装:带卷 (TR) |
| ISL62381HIEVAL1Z | 功能描述:EVALUATION BOARD FOR ISL62381HI RoHS:是 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:Robust Ripple Regulator™ (R³) 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:True Shutdown™ 主要目的:DC/DC，步升 输出及类型:1，非隔离 功率 - 输出:- 输出电压:- 电流 - 输出:1A 输入电压:2.5 V ~ 5.5 V 稳压器拓扑结构:升压 频率 - 开关:3MHz 板类型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
| ISL62381HRTZ | 功能描述:IC PWR SUPPLY CONTROLLER 32TQFN RoHS:是 类别:集成电路 (IC) >> PMIC - 电源控制器，监视器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 应用:多相控制器 输入电压:- 电源电压:9 V ~ 14 V 电流 - 电源:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:40-WFQFN 裸露焊盘 供应商设备封装:40-TQFN-EP（5x5） 包装:带卷 (TR) |
| ISL62381HRTZ-T | 功能描述:IC PWR SUPPLY CONTROLLER 32TQFN RoHS:是 类别:集成电路 (IC) >> PMIC - 电源控制器，监视器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 应用:多相控制器 输入电压:- 电源电压:9 V ~ 14 V 电流 - 电源:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:40-WFQFN 裸露焊盘 供应商设备封装:40-TQFN-EP（5x5） 包装:带卷 (TR) |
| ISL62381LOEVAL1Z | 功能描述:EVALUATION BOARD FOR ISL62381LO RoHS:是 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:Robust Ripple Regulator™ (R³) 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:True Shutdown™ 主要目的:DC/DC，步升 输出及类型:1，非隔离 功率 - 输出:- 输出电压:- 电流 - 输出:1A 输入电压:2.5 V ~ 5.5 V 稳压器拓扑结构:升压 频率 - 开关:3MHz 板类型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
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