参数资料
| 型号： | ISL62386HIEVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 12/20页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR ISL62386HI 32TQFN |
| 标准包装： | 1 |
| 系列： | * |
ISL62386
Theory of Operation
Four Output Controller
The ISL62386 generates four regulated output voltages,
including two PWM controllers and two LDOs. The two PWM
frequency is proportional to the slew rates of the positive and
negative slopes of V R; it is inversely proportional to the
voltage between V W and V COMP . Equation 3 illustrates how
to calculate the window size based on output voltage and
frequency set resistor R W .
channels are identical and almost entirely independent.
Unless otherwise stated, only one individual channel is
V W = g m ? V OUT ? ( 1 – D ) ? R W
(EQ. 3)
(EQ. 4)
F SW = ---------------------------------
discussed, and the conclusion applies to both channels.
PWM Modulator
The ISL62386 modulator features Intersil’s R 3 technology, a
hybrid of fixed frequency PWM control and variable
frequency hysteretic control. Intersil’s R 3 technology can
simultaneously affect the PWM switching frequency and
PWM duty cycle in response to input voltage and output load
transients. The R 3 modulator synthesizes an AC signal V R ,
which is an analog representation of the output inductor
Programming the PWM Switching Frequency
The ISL62386 does not use a clock signal to produce
PWMs. The PWM switching frequency F SW is programmed
by the resistor R W that is connected from the FSET pin to
the GND pin. The approximate PWM switching frequency
can be expressed as written in Equation 4:
1
10 ? C R ? R W
For a desired F SW , the R W can be selected by Equation 5.
R W = ------------------------------------
ripple current. The duty-cycle of V R is the result of charge
and discharge current through a ripple capacitor C R . The
1
10 ? C R ? F SW
(EQ. 5)
current through C R is provided by a transconductance
amplifier g m that measures the VIN and VO pin voltages.
The positive slope of V R can be written as Equation 1:
where C R = 17pF with ±20% error range. To smooth the
FSET pin voltage, a ceramic capacitor such as 10nF is
necessary to parallel with R W.
V RPOS = g m ? ( V IN – V OUT ) ? C R
(EQ. 1)
It is recommended that whenever the control loop
compensation network is modified, F SW should be checked
The negative slope of V R can be written as Equation 2:
for the correct frequency and if necessary, adjust R W .
V RNEG = g m ? V OUT ? C R
(EQ. 2)
Power-On Reset
Where g m is the gain of the transconductance amplifier.
The ISL62386 is disabled until the voltage at the VIN pin has
increased above the rising power-on reset (POR) threshold
voltage. The controller will be disabled when the voltage at
the VIN pin decreases below the falling POR threshold.
RIPPLE CAPACITOR VOLTAGE V R
WINDOW VOLTAGE V W
(WRT V COMP )
ERROR AMPLIFIER
VOLTAGE V COMP
PWM
In addition to VIN POR, the LDO5 pin is also monitored. If its
voltage falls below 4.2V, the SMPS outputs will be shut
down. This ensures that there is sufficient BOOT voltage to
enhance the upper MOSFET.
EN, Soft-Start and PGOOD
The ISL62386 uses a digital soft-start circuit to ramp the
output voltage of each SMPS to the programmed regulation
setpoint at a predictable slew rate. The slew rate of the
soft-start sequence has been selected to limit the in-rush
current through the output capacitors as they charge to the
desired regulation voltage. When the EN pins are pulled
above their rising thresholds, the PGOOD Soft-Start Delay,
FIGURE 23. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
A window voltage V W is referenced with respect to the error
amplifier output voltage V COMP , creating an envelope into
which the ripple voltage V R is compared. The amplitude of
V W is set by a resistor connected across the FSET and GND
pins. The V R, V COMP, and V W signals feed into a window
comparator in which V COMP is the lower threshold voltage
and V COMP + V W is the higher threshold voltage. Figure 23
shows PWM pulses being generated as V R traverses the
V COMP and V COMP + V W thresholds. The PWM switching
12
t SS , starts and the output voltage begins to rise. The FB pin
ramps to 0.6V in approximately 1.5ms and the PGOOD pin
goes to high impedance approximately 1.25ms after the FB
pin voltage reaches 0.6V.
The PGOOD pin indicates when the converter is capable of
supplying regulated voltage. It is an undefined impedance if
V IN is not above the rising POR threshold or below the POR
falling threshold. When a fault is detected, the ISL62386 will
turn on the open-drain NMOS, which will pull PGOOD low
with a nominal impedance of 32 Ω. This will flag the system
that one of the output voltages is out of regulation.
FN6831.0
February 4, 2009
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