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| 型号： | ISL6261AEVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 15/34页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 1 FOR ISL6261A |
| 标准包装： | 1 |
| 系列： | * |
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ISL6261A
High Efficiency Operation Mode
The operational modes of the ISL6261A depend on the
control signal states of DPRSTP#, FDE, and DPRSLPVR, as
shown in Table 2. These control signals can be tied to lntel ?
IMVP-6 ? control signals to maintain the optimal system
configuration for all IMVP-6 ? conditions.
DPRSTP# = 0, FDE = 0 and DPRSLPVR = 1 enables the
ISL6261A to operate in Diode Emulation Mode (DEM) by
monitoring the low-side FET current. In diode emulation
mode, when the low-side FET current flows from source to
drain, it turns on as a synchronous FET to reduce the
conduction loss. When the current reverses its direction, trying
to flow from drain to source, the ISL6261A turns off the
low-side FET to prevent the output capacitor from discharging
through the inductor, therefore eliminating the extra
conduction loss. When DEM is enabled, the regulator works in
automatic Discontinuous Conduction Mode (DCM), meaning
that the regulator operates in CCM in heavy load, and
operates in DCM in light load. DCM in light load decreases the
switching frequency to increase efficiency. This mode can be
used to support the deeper sleep mode of the microprocessor.
DPRSTP# = 0 and FDE = 1 enables the Enhanced Diode
Emulation Mode (EDEM), which increases the VW-COMP
window voltage by 33%. This further decreases the
switching frequency at light load to boost efficiency in the
deeper sleep mode.
For other combinations of DPRSTP#, FDE, and
DPRSLPVR, the ISL6261A operates in forced CCM.
The ISL6261A operational modes can be set according to
CPU mode signals to achieve the best performance. There
are two options: (1) Tie FDE to DPRSLPVR, and tie
DPRSTP# and DPRSLPVR to the corresponding CPU mode
signals. This configuration enables EDEM in deeper sleep
mode to increase efficiency. (2) Tie FDE to “1” and
DPRSTP# to “0” permanently, and tie DPRSLPVR to the
corresponding CPU mode signal. This configuration sets the
regulator in EDEM all the time. The regulator will enter DCM
based on load current. Light-load efficiency is increased in
both active mode and deeper sleep mode.
CPU mode-transition sequences often occur in concert with
VID changes. The ISL6261A employs carefully designed
mode-transition timing to work in concert with the VID changes.
The ISL6261A is equipped with internal counters to prevent
control signal glitches from triggering unintended mode
transitions. For example: Control signals lasting less than
seven switching periods will not enable the diode emulation
mode.
Dynamic Operation
The ISL6261A responds to VID changes by slewing to new
voltages with a dv/dt set by the SOFT capacitor and the logic of
DPRSLPVR. If C SOFT = 20nF and DPRSLPVR = 0, the output
voltage will move at a maximum dv/dt of ±10mV/ μ s for large
changes. The maximum dv/dt can be used to achieve fast
recovery from Deeper Sleep to Active mode. If C SOFT = 20nF
and DPRSLPVR = 1, the output voltage will move at a dv/dt of
±2mV/ μ s for large changes. The slow dv/dt into and out of
deeper sleep mode will minimize the audible noise. As the
output voltage approaches the VID command value, the dv/dt
moderates to prevent overshoot. The ISL6261A is IMVP-6 ?
compliant for DPRSTP# and DPRSLPVR logic.
Intersil R 3 ? has an intrinsic voltage feed forward function.
High-speed input voltage transients have little effect on the
output voltage.
Intersil R 3 ? commands variable switching frequency during
transients to achieve fast response. Upon load application,
the ISL6261A will transiently increase the switching
frequency to deliver energy to the output more quickly.
Compared with steady state operation, the PWM pulses
during load application are generated earlier, which
effectively increases the duty cycle and the response speed
of the regulator. Upon load release, the ISL6261A will
transiently decrease the switching frequency to effectively
reduce the duty cycle to achieve fast response.
TABLE 3. FAULT-PROTECTION SUMMARY OF ISL6261A
FAULT DURATION
FAULT TYPE
Overcurrent fault
Way-Overcurrent fault
Overvoltage fault (1.7V)
PRIOR TO PROTECTION
120μs
<2μs
Immediately
PROTECTION ACTIONS
PWM tri-state, PGOOD latched low
PWM tri-state, PGOOD latched low
Low-side FET on until Vcore < 0.85V, then
FAULT RESET
VR_ON toggle or VDD toggle
VR_ON toggle or VDD toggle
VDD toggle
PWM tri-state, PGOOD latched low
(OV-1.7V always)
Overvoltage fault (+200mV)
Undervoltage fault (-300mV)
1ms
1ms
PWM tri-state, PGOOD latched low
PWM tri-state, PGOOD latched low
VR_ON toggle or VDD toggle
VR_ON toggle or VDD toggle
Over-temperature fault (NTC<1.18) Immediately
15
VR_TT# goes high
N/A
FN6354.3
November 5, 2009
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| ISL6261AEVAL2Z | 功能描述:EVAL BOARD 2 FOR ISL6261A RoHS:是 类别:编程器，开发系统 >> 评估板 - 线性稳压器 (LDO) 系列:* 产品变化通告:1Q2012 Discontinuation 30/Mar/2012 设计资源:NCP590MNDPTAGEVB Gerber Files 标准包装:1 系列:- 每 IC 通道数:2 - 双 输出电压:1.8V，2.8V 电流 - 输出:300mA 输入电压:2.1 ~ 5.5 V 稳压器类型:正，固定式 工作温度:-40°C ~ 85°C 板类型:完全填充 已供物品:板 已用 IC / 零件:NCP590MNDP 其它名称:NCP590MNDPTAGEVB-NDNCP590MNDPTAGEVBOS |
| ISL6261AIRZ | 功能描述:DC/DC 开关控制器 ONE-PHS INT DC/DC BUCK CNTRLR IMVP-6 RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| ISL6261AIRZ-T | 功能描述:DC/DC 开关控制器 ONE-PHS INT DC/DC BUCK CNTRLR IMVP-6 RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| ISL6261CR7Z | 功能描述:IC CTRLR BUCK 1PHASE 48-VFQFN EP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6261CR7Z-T | 功能描述:IC CTRLR BUCK 1PHASE 48-VFQFN-EP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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