参数资料
型号: ISL6263BHRZ-T
厂商: Intersil
文件页数: 13/18页
文件大小: 0K
描述: IC DC/DC BUCK CTRLR 1PH 32-QFN
标准包装: 6,000
应用: 转换器,Intel IMVP-6
输入电压: 5 V ~ 25 V
输出数: 1
输出电压: 0.41 V ~ 1.29 V
工作温度: -10°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN(5x5)
包装: 带卷 (TR)
ISL6263B
The minimum value of the bootstrap capacitor can be
calculated using Equation 3:
RBIAS Current Reference
The RBIAS pin is internally connected to a 1.545V reference
C BOOT ≥ ------------------------
Q GATE
Δ V BOOT
(EQ. 3)
through a 3k Ω resistance. A bias current is established by
connecting a ± 1% tolerance, 150k Ω resistor between the
RBIAS and VSS pins. This bias current is mirrored, creating the
( T – 0.5 × 10
)
R FSET = -----------------------------------------
400 × 10
where Q GATE is the amount of gate charge required to fully
charge the gate of the upper MOSFET. The Δ V BOOT term is
defined as the allowable droop in the rail of the upper drive.
As an example, suppose an upper MOSFET has a gate
charge, Q GATE , of 25nC at 5V and also assume the droop in
the drive voltage at the end of a PWM cycle is 200mV. One
will find that a bootstrap capacitance of at least 0.125μF is
required. The next larger standard value capacitance is
0.15μF. A good quality ceramic capacitor is recommended.
Soft-Start and Soft Dynamic VID Slew Rates
The output voltage of the converter tracks V SOFT, the
voltage across the SOFT and VSS pins. Shown in Figure 1,
the SOFT pin is connected to the output of the VID DAC
through the unidirectional soft-start current source I SS or the
bidirectional soft-dynamic VID current source I DVID , and the
non-inverting input of the error amplifier. Current is sourced
from the SOFT pin when I SS is active. The SOFT pin can
both source and sink current when I DVID is active. The
soft-start capacitor C SOFT changes voltage at a rate
proportional to I SS or I DVID . The ISL6263B automatically
selects I SS for the soft-start sequence so that the inrush
current through the output capacitors is maintained below
the OCP threshold. Once soft-start has completed, I DVID is
automatically selected for output voltage changes
reference current I OCSET that is sourced from the OCSET pin.
Do not connect any other components to this pin, as they will
have a negative impact on the performance of the IC.
Setting the PWM Switching Frequency
The R 3 modulator scheme is not a fixed-frequency
architecture, lacking a fixed-frequency clock signal to
produce PWM. The switching frequency increases during
the application of a load to improve transient performance.
The static PWM frequency varies slightly depending on the
input voltage, output voltage, and output current, but this
variation is normally less than 10% in continuous conduction
mode.
Refer to Figure 2 and find that resistor R FSET is connected
between the V W and COMP pins. A current is sourced from
VW through R FSET creating the synthetic ripple window
voltage signal V W which determines the PWM switching
frequency. The relationship between the resistance of R FSET
and the switching frequency in CCM is approximated by
Equation 6:
– 6
(EQ. 6)
– 12
For example, the value of R FSET for 300kHz operation is
approximately:
( 3.33 × 10
– 0.5 × 10
)
7.1 × 10 = --------------------------------------------------------------------
400 × 10
commanded by the VID inputs, charging C SOFT when the
output voltage is commanded to rise, and discharging
C SOFT when the output voltage is commanded to fall.
3
– 6 – 6
– 12
(EQ. 7)
C SOFT = ------------------------- = ------------------ = 0.018 μ F
? 10mV - ?
? μ s ?
(EQ. 4)
The IMVP-6+ Render Voltage Regulator specification
requires a minimum of 10mV/μs for SLEWRATE GFX . The
value for C SOFT must guarantee the minimum slew-rate of
10mV/μs when the soft-dynamic VID current source I DVID is
the minimum specified value in the “Electrical Specifications”
table on page 7. The value of C SOFT , can be calculated
using Equation 4:
I DVIDmin 180 μ A
10K
---------------
Choosing the next lower standard component value of
0.015μF will guarantee 10mV/μs SLEWRATE GFX . This
choice of C SOFT controls the startup slew-rate as well. One
should expect the output voltage during soft-start to slew to
the voltage commanded by the VID settings at a nominal
rate given by Equation 5:
This relationship only applies to operation in constant
conduction mode because the PWM frequency naturally
decreases as the load decreases while in diode emulation
mode.
Static Droop Design Using DCR Sensing
The ISL6263B has an internal differential amplifier to
accurately regulate the voltage at the processor die.
For DCR sensing, the process to compensate the DCR
resistance variation takes several iterative steps. Figure 2
shows the DCR sensing method. Figure 8 shows the
simplified model of the droop circuitry. The inductor DC
current generates a DC voltage drop on the inductor DCR.
Equation 8 gives this relationship
V DCR = I o ? DCR (EQ. 8)
dV SOFT I SS 42 μ A 2.8mV
0.015 μ F
μ s
----------------------- = ------------------- = ----------------------- ≈ ------------------
C SOFT
dt
Note that the slewrate is the average rate of change
between the initial and final voltage values.
13
(EQ. 5)
An R-C network senses the voltage across the inductor to
get the inductor current information. R NTCEQ represents the
NTC network consisting of R NTC , R NTCS, and R NTCP . The
choice of R S will be discussed in the next section.
FN6388.3
July 8, 2010
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