参数资料
型号: ISL6271ACRZ-T
厂商: Intersil
文件页数: 15/16页
文件大小: 0K
描述: IC PMIC XSCALE REG 20-QFN
标准包装: 1
应用: 处理器
电流 - 电源: 380µA
电源电压: 2.76 V ~ 5.5 V
工作温度: -25°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-VFQFN 裸露焊盘
供应商设备封装: 20-QFN 裸露焊盘(4x4)
包装: 标准包装
产品目录页面: 1248 (CN2011-ZH PDF)
其它名称: ISL6271ACRZ-TDKR
ISL6271A
Internal ESD Structures
The ISL6271A input/output pins are protected from over-
Layout Recommendation
voltage conditions by clamping the pin to one diode drop
above or below the VCC voltage rail. During shutdown it is
possible that the SDA and SCL pins have a voltage greater
than VCC. Under this condition, the ESD diodes will provide
a reverse current path to circuitry on VCC that can act as a
LDO
OUTPUT
CAPS
SINGLE
PT. GND
FB RES
OUTPUT CAP
load on the back-up battery. To avoid this condition, interrupt
VCC from external circuitry if a voltage greater than VCC is
expected on any of the pins identified below.
OUTPUT
INDUCTOR
5x5x1mm
PGND
GND
SOFT-START
CAP
PVCC INPUT CAP
BBAT
VCC
SDA
SCL
EN
VPLL
VSRAM
SOFT
GND
GND
PVCC
LVCC
VOUT
FB
PGOOD
BFLT#
VCC LPF
FIGURE 27. COMPONENT PLACEMENT AND TOP COPPER
Since the ISL6271A can operate at a high switching
frequency, it is especially important to apply good layout
practices. Decoupling of the regulator ’s input voltage
(PVCC) and minimizing the loop area associated with the
phase node output filter is essential for reliable operation.
Return currents from the load should find a low impedance
path to the PGND pin on the IC (Pin 8). Ideally, the core
voltage would be distributed to the embedded processor on
a low impedance power plane; however, a 30-50mil, short
trace should be sufficient. When implementing DVM it is
important to minimize inductance between the load and the
output filter. The processors can command slew rates of up
to 200mA/ns and local decoupling at the processor socket is
essential to satisfying this requirement.
References
[1] ISL6292 data sheet - Battery Charger
[2] EL7536 data sheet - System regulator
[3] C-Code examples for PWR_I2C bus communication -
Intersil support documentation available upon request.
FIGURE 26. INTERNAL ESD STRUCTURES
15
[4] PHILLIPS I 2 C BUS Specification
[5] http://www.semiconductors.philips.com/buses/i2c/
[6] Technical Brief TB389 “ PCB Land Pattern Design and
Surface Mount Guidelines for MLF Packages”
FN9171.1
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