参数资料
| 型号： | ISL62771IRTZ-T |
| 厂商： | Intersil |
| 文件页数： | 24/36页 |
| 文件大小： | 0K |
| 描述： | IC PWM CTRLR MULTIPHASE 40TQFN |
| 标准包装： | 6,000 |
| 系列： | Robust Ripple Regulator™ (R³) |
| 应用： | 控制器，AMD Fusion? SVI 2.0 CPU GPU |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 2 |
| 输出电压： | 0.006 V ~ 1.55 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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ISL62771
The AMD processor bus protocol is compliant with SMBus send
byte protocol for VID transactions. The AMD SVD packet structure
is shown in Figure 17. The description of what each bit of the
FUNCTION
TABLE 9. PSI0_L, PSI1_L and TFN DEFINITION
Bit DESCRIPTION
three bytes that make up the SVI command are shown in Table 8.
During a transaction, the processor sends the start sequence
followed by each of the three bytes, which end with an optional
acknowledge bit. The ISL62771 does not drive the SVD line
during the ACK bit. Finally, the processor sends the stop
sequence. After the ISL62771 has detected the stop, it can then
proceed with the commanded action from the transaction.
TABLE 8. SVD DATA PACKET
BITS
DESCRIPTION
PSI0_L
PSI1_L
10
20
Power State Indicate level 0. When this signal is
asserted (active Low) the processor is in a low
enough power state for the VR controller to take
action to boost efficiency by dropping phases and/or
entering 1-Phase DE.
Power State Indicate level 1. When this signal is
asserted (active Low) the processor is in a low
enough power state for the VR controller to take
action to boost efficiency by dropping phases and
entering 1-Phase DE
1:5
6
Always 11000b
Core domain selector bit, if set then the following data byte
contains VID, power state, telemetry control, load line trim and
TFN
21
Telemetry Functionality. This is an active high signal
that allows the processor to control the telemetry
functionality of the VR.
offset trim apply to the Core VR.
Dynamic Load Line Slope Trim
7
8
9
10
Northbridge domain selector bit, if set then the following data
byte contains VID, power state, telemetry control, load line trim
and offset trim apply to the Northbridge VR.
Always 0b
Acknowledge Bit
PSI0_L
The ISL62771 supports the SVI2 ability for the processor to
manipulate the load line slope of the Core and Northbridge VRs
independently using the serial VID interface. The slope
manipulation applies to the initial load line slope. A load line
slope trim will typically coincide with a VOTF change. See Table
10 for more information about the load line slope trim feature of
the ISL62771.
11:17 VID Code bits [7:1]
TABLE 10. LOAD LINE SLOPE TRIM DEFINITION
18
Acknowledge Bit
LOAD LINE
19
20
21
VID Code bit [0]
PSI1_L
TFN (Telemetry Functionality)
SLOPE TRIM [2:0]
000
001
010
Disable LL
-40% m Ω Change
-20% m Ω Change
DESCRIPTION
22:24 Load Line Slope Trim
25:26 Offset Trim [1:0]
011
100
No Change
+20% m Ω Change
27
Acknowledge Bit
101
+40% m Ω Change
Power States
110
111
+60% m Ω Change
+80% m Ω Change
SVI2 defines two power state indicator levels, see Table 9. As
processor current consumption reduces the power state indicator
level changes to improve VR efficiency under low power
conditions.
For the Core VR operating in 2-phase mode, when PSI0_L is
asserted, Channel 2 is tri-stated and Channel 1 enters diode
emulation mode to boost efficiency. When PSI0_L and PSI1_L
are asserted low, the Core VR continues to operate in this mode.
For the 1-Phase Northbridge VR, when PSI0_L is asserted,
Dynamic Offset Trim
The ISL62771 supports the SVI2 ability for the processor to
manipulate the output voltage offset of the Core and Northbridge
VRs. This offset is in addition to any output voltage offset set via
the COMP resistor reader. The dynamic offset trim can disable
the COMP resistor programmed offset of either output when
“Disable All Offset” is selected.
TABLE 11. OFFSET TRIM DEFINITION
Channel 1 enters diode emulation mode to boost efficiency.
When PSI0_L and PSI1_L are asserted low, the Northbridge VR
continues to operate in this fashion.
It is possible for the processor to assert or deassert PSI0_L and
PSI1_L out of order. PSI0_L takes priority over PSI1_L. If PSI0_L
is deasserted while PSI1_L is still asserted, the ISL62771 will
return the selected VR back full channel CCM operation.
24
OFFSET TRIM
[1:0]
00
01
10
11
Disable All Offset
-25mV Change
0mV Change
+25mV Change
DESCRIPTION
FN8321.2
September 12, 2013
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL62773 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Multiphase PWM Regulator for AMD Fusiona?￠ Desktop CPUs Using SVI 2.0 |
| ISL62773HRZ | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLR FOR AMD FUSION UP RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL62773HRZ-T | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLR FOR AMD FUSION UP RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL62773IRZ | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLR FOR AMD FUSION UP RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL62773IRZ-T | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLR FOR AMD FUSION UP RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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