参数资料
| 型号： | ISL62771IRTZ-T |
| 厂商： | Intersil |
| 文件页数： | 9/36页 |
| 文件大小： | 0K |
| 描述： | IC PWM CTRLR MULTIPHASE 40TQFN |
| 标准包装： | 6,000 |
| 系列： | Robust Ripple Regulator™ (R³) |
| 应用： | 控制器，AMD Fusion? SVI 2.0 CPU GPU |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 2 |
| 输出电压： | 0.006 V ~ 1.55 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页
ISL62771
Pin Descriptions (Continued)
PIN NUMBER
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
SYMBOL
ISEN1
ISUMP
ISUMN
VSEN
RTN
FB
COMP
PGOOD
BOOT1
UGATE1
PHASE1
LGATE1
VDD
VDDP
LGATE2
PHASE2
UGATE2
BOOT2
BOOT_NB
UGATE_NB
PHASE_NB
LGATE_NB
PGOOD_NB
9
DESCRIPTION
Individual current sensing for Channel 1 of the Core VR. If ISEN2 is tied to +5V, this pin cannot be left
open and must be tied to GND with a 10k Ω resistor. If ISEN1 is tied to +5V, the Core portion of the IC is
shutdown.
Non-inverting input of the transconductance amplifier for current monitor and load line of Core output.
Inverting input of the transconductance amplifier for current monitor and load line of Core output.
Output voltage sense pin for the Core controller. Connect to the +sense pin of the microprocessor die.
Output voltage sense return pin for both Core VR and Northbridge VR. Connect to the -sense pin of the
microprocessor die.
Output voltage feedback to the inverting input of the Core controller error amplifier.
Core controller error amplifier output. A resistor from COMP to GND sets the Core VR offset voltage.
Open-drain output to indicate the Core portion of the IC is ready to supply regulated voltage. Pull up
externally to VDD or 3.3V through a resistor.
Connect an MLCC capacitor across the BOOT1 and the PHASE1 pins. The boot capacitor is charged,
through an internal boot diode connected from the VDDP pin to the BOOT1 pin, each time the PHASE1
pin drops below VDDP minus the voltage dropped across the internal boot diode.
Output of the Phase 1 high-side MOSFET gate driver of the Core VR. Connect the UGATE1 pin to the gate
of the Phase 1 high-side MOSFET(s).
Current return path for the Phase 1 high-side MOSFET gate driver of VR1. Connect the PHASE1 pin to the
node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of
Phase 1.
Output of the Phase 1 low-side MOSFET gate driver of the Core VR. Connect the LGATE1 pin to the gate
of the Phase 1 low-side MOSFET(s).
5V bias power. A resistor [2 Ω ] and a decoupling capacitor should be used from the +5V supply. A high
quality, X7R dielectric MLCC capacitor is recommended.
Input voltage bias for the internal gate drivers. Connect +5V to the VDDP pin. Decouple with at least 1μF
of capacitance to GND. A high quality, X7R dielectric MLCC capacitor is recommended.
Output of the Phase 2 low-side MOSFET gate driver of the Core VR. Connect the LGATE2 pin to the gate
of the Phase 2 low-side MOSFET(s).
Current return path for the Phase 2 high-side MOSFET gate driver of the Core VR. Connect the PHASE2
pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output
inductor of Phase 2.
Output of the Phase 2 high-side MOSFET gate driver of the Core VR. Connect the UGATE2 pin to the gate
of the Phase 2 high-side MOSFET(s).
Connect an MLCC capacitor across the BOOT2 and PHASE2 pins. The boot capacitor is charged, through
an internal boot diode connected from the VDDP pin to the BOOT2 pin, each time the PHASE2 pin drops
below VDDP minus the voltage dropped across the internal boot diode.
Boot connection of the Northbridge VR. Connect an MLCC capacitor across the BOOT1_NB and the
PHASE_NB pins. The boot capacitor is charged, through an internal boot diode connected from the VDDP
pin to the BOOT_NB pin, each time the PHASE_NB pin drops below VDDP minus the voltage dropped
across the internal boot diode.
High-side MOSFET gate driver of the Northbridge VR. Connect the UGATE_NB pin to the gate of the
high-side MOSFET(s) of the Northbridge VR.
Phase connection of the Northbridge VR. Current return path for the high-side MOSFET gate driver of the
floating internal driver. Connect the PHASE_NB pin to the node consisting of the high-side MOSFET
source, the low-side MOSFET drain, and the output inductor of the Northbridge VR.
Low-side MOSFET gate driver of the Northbridge VR. Connect the LGATE_NB pin to the gate of the low-side
MOSFET(s) of the Northbridge VR.
Open-drain output to indicate the Northbridge portion of the IC is ready to supply regulated voltage.
Pull-up externally to VDDP or 3.3V through a resistor.
FN8321.2
September 12, 2013
相关PDF资料 |
PDF描述 |
|---|---|
| X40034V14-BT1 | IC VOLTAGE MONITOR TRPL 14-TSSOP |
| RYM30DRSH-S288 | CONN EDGECARD 60POS .156 EXTEND |
| X40034V14-B | IC VOLTAGE MONITOR TRPL 14-TSSOP |
| 420MXG390MEFCSN30X40 | CAP ALUM 390UF 420V 20% SNAP-IN |
| RMM30DRSH-S288 | CONN EDGECARD 60POS .156 EXTEND |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL62773 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Multiphase PWM Regulator for AMD Fusiona?￠ Desktop CPUs Using SVI 2.0 |
| ISL62773HRZ | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLR FOR AMD FUSION UP RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL62773HRZ-T | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLR FOR AMD FUSION UP RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL62773IRZ | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLR FOR AMD FUSION UP RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL62773IRZ-T | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLR FOR AMD FUSION UP RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
发布紧急采购，3分钟左右您将得到回复。