参数资料
| 型号： | ISL6277IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 14/37页 |
| 文件大小： | 0K |
| 描述： | IC PWM REG MULTIPH AMD 48-QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD Fusion? SVI 2.0 CPU GPU |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 2 |
| 输出电压： | 0.006 V ~ 1.55 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页当前第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页
ISL6277
Theory of Operation
VW
Multiphase R 3 ? Modulator
The ISL6277 is a multiphase regulator implementing two voltage
regulators, CORE VR and Northbridge (NB) VR, on one chip
controlled by AMD’s? SVI2? protocol. The CORE VR can be
programmed for 1-, 2- or 3-phase operation. The Northbridge VR
can be configured for 1- or 2-phase operation. Both regulators use
the Intersil patented R 3 ? (Robust Ripple Regulator) modulator.
The R 3 ? modulator combines the best features of fixed frequency
PWM and hysteretic PWM while eliminating many of their
shortcomings. Figure 7 conceptually shows the multiphase R 3 ?
modulator circuit, and Figure 8 shows the operation principles.
MASTER CLOCK CIRCUIT
VW
MASTER
VCRM
COMP
MASTER
CLOCK
CLOCK1
PWM1
CLOCK2
PWM2
HYSTERETIC
WINDOW
MASTER
CLOCK
GMVO
COMP
VCRM
CRM
CLOCK
PHASE
SEQUENCER
CLOCK1
CLOCK2
CLOCK3
CLOCK3
PWM3
VW
SLAVE CIRCUIT 1
VW
CLOCK1
S
R
Q
PWM1
PHASE1
L1
I L1
VO
CO
VCRS2
VCRS3
VCRS1
CRS1
VCRS1
GM
FIGURE 8. R 3 ? MODULATOR OPERATION PRINCIPLES IN
STEADY STATE
VW
SLAVE CIRCUIT 2
CLOCK2 S PWM2
Q
R
PHASE2
L2
I L2
Each slave circuit has its own ripple capacitor C rs , whose voltage
mimics the inductor ripple current. A g m amplifier converts the
inductor voltage into a current source to charge and discharge
CRS2
VCRS2
VW
GM
CLOCK3
SLAVE CIRCUIT 3
S PWM3
Q
R
PHASE3
L3
I L3
C rs . The slave circuit turns on its PWM pulse upon receiving the
clock signal, and the current source charges C rs . When C rs
voltage V Crs hits VW, the slave circuit turns off the PWM pulse,
and the current source discharges C rs .
Since the controller works with V crs , which are large amplitude
and noise-free synthesized signals, it achieves lower phase jitter
CRS3
VCRS3
GM
FIGURE 7. R 3 ? MODULATOR CIRCUIT
than conventional hysteretic mode and fixed PWM mode
controllers. Unlike conventional hysteretic mode converters, the
error amplifier allows the ISL6277 to maintain a 0.5% output
voltage accuracy.
Figure 9 shows the operation principles during load insertion
response. The COMP voltage rises during load insertion,
Inside the IC, the modulator uses the master clock circuit to
generate the clocks for the slave circuits. The modulator
discharges the ripple capacitor C rm with a current source equal
to g m V o , where g m is a gain factor. C rm voltage V CRM is a
sawtooth waveform traversing between the VW and COMP
voltages. It resets to VW when it hits COMP, and generates a
one-shot master clock signal. A phase sequencer distributes the
master clock signal to the slave circuits. If the CORE VR is in
3-phase mode, the master clock signal is distributed to the three
phases, and the Clock 1~3 signals will be 120° out-of-phase. If
the Core VR is in 2-phase mode, the master clock signal is
distributed to Phases 1 and 2, and the Clock1 and Clock2 signals
will be 180° out-of-phase. If the Core VR is in 1-phase mode, the
master clock signal will be distributed to Phase 1 only and be the
Clock1 signal.
14
generating the master clock signal more quickly, so the PWM
pulses turn on earlier, increasing the effective switching
frequency. This allows for higher control loop bandwidth than
conventional fixed frequency PWM controllers. The VW voltage
rises as the COMP voltage rises, making the PWM pulses wider.
During load release response, the COMP voltage falls. It takes
the master clock circuit longer to generate the next master clock
signal so the PWM pulse is held off until needed. The VW voltage
falls as the COMP voltage falls, reducing the current PWM pulse
width. This kind of behavior gives the ISL6277 excellent response
speed.
The fact that all the phases share the same VW window voltage
also ensures excellent dynamic current balance among phases.
FN8270.1
March 8, 2012
相关PDF资料 |
PDF描述 |
|---|---|
| ADP1716ARMZ-1.3-R7 | IC REG LDO 1.3V .5A 8MSOP |
| ISL62773HRZ-T | IC PWM REG MULTIPH AMD 48-QFN |
| HSC12DRAN | CONN EDGECARD 24POS R/A .100 SLD |
| EMC28DREI-S13 | CONN EDGECARD 56POS .100 EXTEND |
| ADP3335ARMZ-3.3RL7 | IC REG LDO 3.3V .5A 8-MSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL62810AHRUZ-T | 制造商:Intersil Corporation 功能描述:0/2-BIT PWM GPU CONTROLLER FOR NOTEBOOK. 20 LD 3.2 X 1.8 UTQ - Tape and Reel 制造商:Intersil 功能描述:0/2 BIT PWM GPU CONTLR FOR NOTEBOOK |
| ISL62810HRUZ-T | 制造商:Intersil Corporation 功能描述:0/2-BIT PWM GPU CONTROLLER FOR NOTEBOOK. 16LD 2.6 X 1.8 UTQF - Tape and Reel 制造商:Intersil 功能描述:0/2 BIT PWM GPU CONTLR FOR NOTEBOOK |
| ISL62870 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:PWM DC/DC Voltage Regulator Controller |
| ISL62870HRUZ | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:PWM DC/DC Voltage Regulator Controller |
| ISL62870HRUZ-T | 功能描述:IC REG CTRLR BUCK PWM 16-TQFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:Robust Ripple Regulator™ (R³) 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
发布紧急采购，3分钟左右您将得到回复。