参数资料
| 型号： | ISL6277IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 34/37页 |
| 文件大小： | 0K |
| 描述： | IC PWM REG MULTIPH AMD 48-QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD Fusion? SVI 2.0 CPU GPU |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 2 |
| 输出电压： | 0.006 V ~ 1.55 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 带卷 (TR) |
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ISL6277
TABLE 14. LAYOUT CONSIDERATIONS FOR THE ISL6277 CONTROLLER (Continued)
ISL6277 PIN
13
14
15
SYMBOL
ISEN3
ISEN2
ISEN1
LAYOUT GUIDELINES
Each ISEN pin has a capacitor (C isen ) decoupling it to VSUMN and then through another capacitor (C vsumn ) to
GND. Place Cisen capacitors as close as possible to the controller and keep the following loops small:
1. Any ISEN pin to another ISEN pin
2. Any ISEN pin to GND
The red traces in the following drawing show the loops to be minimized.
Phase1
L3
Ro
Risen
ISEN3
Cisen
Phase2
Risen
L2
Ro
Vo
ISEN2
Cisen
Phase3
Risen
L1
Ro
ISEN1
GND
Cisen
Vsumn
Cvsumn
16
17
18
19
20
21
22
23
24
25
26
ISUMP
ISUMN
VSEN
RTN
FB2
FB
COMP
PGOOD
BOOT1
UGATE1
PHASE1
34
Place the current sensing circuit in general proximity of the controller.
Place capacitor Cn very close to the controller.
Place the NTC thermistor next to Core VR Channel 1 inductor so it senses the inductor temperature correctly.
Each phase of the power stage sends a pair of VSUMP and VSUMN signals to the controller. Run these two
signals traces in parallel fashion with decent width (>20mil).
IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. If possible, route the
traces on a different layer from the inductor pad layer and use vias to connect the traces to the center of the
pads. If no via is allowed on the pad, consider routing the traces into the pads from the inside of the inductor.
The following drawings show the two preferred ways of routing current sensing traces.
INDUCTOR
INDUCTOR
VIAS
CURRENT-SENSING TRACES
CURRENT-SENSING TRACES
Place the filter on these pins in close proximity to the controller for good coupling.
Place the compensation components in general proximity of the controller.
No special consideration.
Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this
trace.
These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid
routing these signals near sensitive analog signal traces or crossing over them. Routing PHASE1 to the Core VR
Channel 1 high-side MOSFET source pin instead of a general connection to PHASE1 copper is recommended for
better performance.
FN8270.1
March 8, 2012
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