参数资料
| 型号： | ISL6277IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 35/37页 |
| 文件大小： | 0K |
| 描述： | IC PWM REG MULTIPH AMD 48-QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD Fusion? SVI 2.0 CPU GPU |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 2 |
| 输出电压： | 0.006 V ~ 1.55 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 带卷 (TR) |
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ISL6277
TABLE 14. LAYOUT CONSIDERATIONS FOR THE ISL6277 CONTROLLER (Continued)
ISL6277 PIN
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
SYMBOL
LGATE1
PWM_Y
VDD
VDDP
LGATE2
PHASE2
UGATE2
BOOT2
VIN
BOOTX
UGATEX
PHASEX
LGATEX
PWM2_NB
FCCM_NB
PGOOD_NB
COMP_NB
FB_NB
VSEN_NB
ISUMN_NB
ISUMP_NB
ISEN1_NB
35
LAYOUT GUIDELINES
Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing
over them.
No special considerations.
A high quality, X7R dielectric MLCC capacitor is recommended to decouple this pin to GND. Place the capacitor
in close proximity to the pin with the filter resistor nearby the IC.
A high quality, X7R dielectric MLCC capacitor is recommended to decouple this pin to GND. Place the capacitor
in close proximity to the pin.
Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing
over them.
These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid
routing these signals near sensitive analog signal traces or crossing over them. Routing PHASE2 to the Core VR
Channel 2 high-side MOSFET source pin instead of a general connection to PHASE2 copper is recommended for
better performance.
Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this
trace.
Place the decoupling capacitor in close proximity to the pin with a short connection to the internal GND plane.
Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this
trace.
These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid
routing these signals near sensitive analog signal traces or crossing over them. Routing PHASEX to the high-side
MOSFET source pin instead of a general connection to the PHASEX copper is recommended for better
performance.
Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing
over them.
No special considerations.
No special consideration.
Place the compensation components in general proximity of the controller.
Place the filter on this pin in close proximity to the controller for good coupling.
Place the current sensing circuit in general proximity of the controller.
Place capacitor Cn very close to the controller.
Place the NTC thermistor next to Core VR Channel 1 inductor so it senses the inductor temperature correctly.
Each phase of the power stage sends a pair of VSUMP and VSUMN signals to the controller. Run these two
signals traces in parallel fashion with decent width (>20mil).
IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. If possible, route the
traces on a different layer from the inductor pad layer and use vias to connect the traces to the center of the
pads. If no via is allowed on the pad, consider routing the traces into the pads from the inside of the inductor.
The following drawings show the two preferred ways of routing current sensing traces.
INDUCTOR
INDUCTOR
VIAS
CURRENT-SENSING TRACES
CURRENT-SENSING TRACES
FN8270.1
March 8, 2012
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