参数资料
| 型号： | ISL62870HRUZ-T |
| 厂商： | Intersil |
| 文件页数： | 6/16页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 16-TQFN |
| 标准包装： | 3,000 |
| 系列： | Robust Ripple Regulator™ (R³) |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 330kHz |
| 占空比： | 100% |
| 电源电压： | 3.3 V ~ 25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -10°C ~ 100°C |
| 封装/外壳： | 16-UFQFN |
| 包装： | 带卷 (TR) |
ISL62870
V FB = V OUT ? ----------------------------------
R
+ R
R OFS = -----------------------------------------
Functional Pin Descriptions
GND (Pin 1)
IC ground for bias supply and signal reference.
EN (Pin 2)
Enable input for the IC. Pulling EN above the V ENTHR rising
threshold voltage initializes the soft-start sequence.
NC (Pins 3, 5)
No internal connection. Pins 3 and 5 should be connected to
the GND pin.
SREF (Pin 4)
Soft-start programming capacitor input. Connects internally
to the inverting input of the V SET voltage setpoint amplifier.
PGOOD (Pin 6)
Power-good open-drain indicator output. This pin changes to
high impedance when the converter is able to supply
regulated voltage. The pull-down resistance between the
PGOOD pin and the GND pin identifies which protective fault
FB (Pin 7)
Voltage feedback sense input. Connects internally to the
inverting input of the control-loop error amplifier. The
converter is in regulation when the voltage at the FB pin
equals the voltage on the SREF pin. The control loop
compensation network connects between the FB pin and the
converter output. See Figure 8 on page 10.
VO (Pin 8)
Output voltage sense input for the R 3 modulator. The VO pin
also serves as the reference input for the overcurrent
detection circuit. See Figure 5 on page 7.
OCSET (Pin 9)
Input for the overcurrent detection circuit. The overcurrent
setpoint programming resistor R OCSET connects from this
pin to the sense node. See “OVERCURRENT
PROGRAMMING CIRCUIT” on page 7.
PHASE (Pin 10)
Return current path for the UGATE high-side MOSFET
driver. VIN sense input for the R 3 modulator. Inductor current
polarity detector input. Connect to junction of output inductor,
high-side MOSFET, and low-side MOSFET. See “Application
UGATE (Pin 11)
High-side MOSFET gate driver output. Connect to the gate
terminal of the high-side MOSFET of the converter.
BOOT (Pin 12)
Positive input supply for the UGATE high-side MOSFET gate
driver. The BOOT pin is internally connected to the cathode
6
of the Schottky boot-strap diode. Connect an MLCC
between the BOOT pin and the PHASE pin.
VCC (Pin 13)
Input for the IC bias voltage. Connect +5V to the VCC pin
and decouple with at least a 1μF MLCC to the GND pin. See
PVCC (Pin 14)
Input for the LGATE and UGATE MOSFET driver circuits.
The PVCC pin is internally connected to the anode of the
Schottky boot-strap diode. Connect +5V to the PVCC pin
and decouple with a 10μF MLCC to the PGND pin. See
LGATE (Pin 15)
Low-side MOSFET gate driver output. Connect to the gate
terminal of the low-side MOSFET of the converter.
PGND (Pin 16)
Return current path for the LGATE MOSFET driver. Connect
to the source of the low-side MOSFET.
Setpoint Reference Voltage
The 500mV output of the setpoint reference voltage (V SREF )
appears at the SREF pin. This signal is the output of the
current limited voltage follower that buffers an internal
500mV voltage reference (V REF .) The converter is in
regulation when the voltage at the FB pin (V FB ) equals the
V SREF voltage at the SREF pin. Both of these pins are
measured relative to the GND pin, not the PGND pin.
The feedback voltage-divider network consisting of offset
resistor (R OFS ) and loop-compensation resistor (R FB ) scale
down the converter output voltage (V OUT ) such that the
voltage V FB equals V SREF when V OUT equals the desired
output voltage of the converter. The voltage-divider relation
is given in Equation 1:
R OFS
(EQ. 1)
FB OFS
Where:
- V FB = V SREF
- R FB is the loop-compensation feedback resistor that
connects from the FB pin to the converter output
- R OFS is the voltage-scaling programming resistor that
connects from the FB pin to the GND pin
The value of offset resistor R OFS must be recalculated
whenever the value of loop-compensation resistor R FB has
been changed. Calculation of R OFS is written as shown in
Equation 2:
V SREF ? R FB
(EQ. 2)
V OUT – V SREF
FN6708.0
August 14, 2008
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| ISL62871HRUZ-T | 功能描述:IC REG CTRLR BUCK PWM 16-TQFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:Robust Ripple Regulator™ (R³) 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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