参数资料
| 型号： | ISL62870HRUZ-T |
| 厂商： | Intersil |
| 文件页数： | 8/16页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 16-TQFN |
| 标准包装： | 3,000 |
| 系列： | Robust Ripple Regulator™ (R³) |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 330kHz |
| 占空比： | 100% |
| 电源电压： | 3.3 V ~ 25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -10°C ~ 100°C |
| 封装/外壳： | 16-UFQFN |
| 包装： | 带卷 (TR) |
ISL62870
For example, if I OC is 20A and DCR is 4.5m Ω , the choice of
R OCSET is = 20Ax4.5m Ω /10μA = 9k Ω.
Resistor R OCSET and capacitor C SEN form an R-C network
to sense the inductor current. To sense the inductor current
correctly not only in DC operation, but also during dynamic
operation, the R-C network time constant R OCSET C SEN
needs to match the inductor time constant L/DCR. The value
of C SEN is then written as follows:
below the typical V UVTH threshold of 84% for more than 2μs
in order to trip the UVP fault latch. In numerical terms, that
would be 84% x 1.0V = 0.84V. When a UVP fault is declared,
the PGOOD pin will pull-down to 95 Ω and latch-off the
converter. The fault will remain latched until the EN pin has
been pulled below the falling EN threshold voltage V ENTHF
or if VCC has decayed below the falling POR threshold
voltage V VCC_THF .
C SEN = ------------------------------------------
L
R OCSET ? DCR
(EQ. 9)
Over-Temperature
When the temperature of the IC increases above the rising
VCC_THF . All other protection circuits remain functional
VCC_THF . An OVP fault cannot be reset by pulling the EN
For example, if L is 1.5μH, DCR is 4.5m Ω , and R OCSET is
9k Ω, the choice of C SEN = 1.5μH/(9k Ω x4.5m Ω ) = 0.037μF .
When an OCP fault is declared, the PGOOD pin will
pull-down to 35 Ω and latch off the converter. The fault will
remain latched until the EN pin has been pulled below the
falling EN threshold voltage V ENTHF or if VCC has decayed
below the falling POR threshold voltage V VCC_THF
Overvoltage
The OVP fault detection circuit triggers after the FB pin
voltage is above the rising overvoltage threshold V OVRTH for
more than 2μs. For example, if the converter is programmed
to regulate 1.0V at the FB pin, that voltage would have to
rise above the typical V OVRTH threshold of 116% for more
than 2μs in order to trip the OVP fault latch. In numerical terms,
that would be 116% x 1.0V = 1.16V. When an OVP fault is
declared, the PGOOD pin will pull-down to 65 Ω and latch-off
the converter. The OVP fault will remain latched until VCC
has decayed below the falling POR threshold voltage
V
pin below the falling EN threshold voltage V ENTHF .
Although the converter has latched-off in response to an OVP
fault, the LGATE gate-driver output will retain the ability to
toggle the low-side MOSFET on and off, in response to the
output voltage transversing the V OVRTH and V OVFTH
thresholds. The LGATE gate-driver will turn-on the low-side
MOSFET to discharge the output voltage, protecting the load.
The LGATE gate-driver will turn-off the low-side MOSFET
once the FB pin voltage is lower than the falling overvoltage
threshold V OVRTH for more than 2μs. The falling overvoltage
threshold V OVFTH is typically 102%. That means if the FB pin
voltage falls below 102% x 1.0V = 1.02V, for more than 2μs,
the LGATE gate-driver will turn off the low-side MOSFET. If
the output voltage rises again, the LGATE driver will again
turn on the low-side MOSFET when the FB pin voltage is
above the rising overvoltage threshold V OVRTH for more than
2μs. By doing so, the IC protects the load when there is a
consistent overvoltage condition.
Undervoltage
The UVP fault detection circuit triggers after the FB pin
voltage is below the undervoltage threshold V UVTH for more
than 2μs. For example, if the converter is programmed to
regulate 1.0V at the FB pin, that voltage would have to fall
8
threshold temperature T OTRTH , it will enter the OTP state
that suspends the PWM, forcing the LGATE and UGATE
gate-driver outputs low. The status of the PGOOD pin does
not change nor does the converter latch-off. The PWM
remains suspended until the IC temperature falls below the
hysteresis temperature T OTHYS , at which time normal PWM
operation resumes. The OTP state can be reset if the EN pin
is pulled below the falling EN threshold voltage V ENTHF or if
VCC has decayed below the falling POR threshold voltage
V
while the IC is in the OTP state. It is likely that the IC will
detect an UVP fault because in the absence of PWM, the
output voltage decays below the undervoltage threshold
V UVTH .
Theory of Operation
The modulator features Intersil’s R 3 Robust-Ripple
Regulator technology, a hybrid of fixed frequency PWM
control and variable frequency hysteretic control. The PWM
frequency is maintained at 300kHz under static continuous
conduction mode operation within the entire specified
envelope of input voltage, output voltage, and output load. If
the application should experience a rising load transient
and/or a falling line transient such that the output voltage
starts to fall, the modulator will extend the on-time and/or
reduce the off-time of the PWM pulse in progress.
Conversely, if the application should experience a falling
load transient and/or a rising line transient such that the
output voltage starts to rise, the modulator will truncate the
on-time and/or extend the off-time of the PWM pulse in
progress. The period and duty cycle of the ensuing PWM
pulses are optimized by the R 3 modulator for the remainder
of the transient and work in concert with the error amplifier
V ERR to maintain output voltage regulation. Once the
transient has dissipated and the control loop has recovered,
the PWM frequency returns to the nominal static 300kHz.
Modulator
The R 3 modulator synthesizes an AC signal V R , which is an
analog representation of the output inductor ripple current.
The duty-cycle of V R is the result of charge and discharge
current through a ripple capacitor C R . The current through
C R is provided by a transconductance amplifier g m that
measures the input voltage (V IN ) at the PHASE pin and
FN6708.0
August 14, 2008
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相关代理商/技术参数 |
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| ISL62871 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:PWM DC/DC Controller With VID Inputs For Portable GPU Core-Voltage Regulator |
| ISL62871HRUZ | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:PWM DC/DC Controller With VID Inputs For Portable GPU Core-Voltage Regulator |
| ISL62871HRUZ-T | 功能描述:IC REG CTRLR BUCK PWM 16-TQFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:Robust Ripple Regulator™ (R³) 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL62872HRUZ | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:PWM DC/DC Controller With VID Inputs For Portable GPU Core-Voltage Regulator |
| ISL62872HRUZ-T | 功能描述:IC REG CTRLR BUCK PWM 20-TQFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:Robust Ripple Regulator™ (R³) 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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