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| 型号： | ISL6307CRZ |
| 厂商： | Intersil |
| 文件页数： | 22/34页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 48-QFN |
| 标准包装： | 43 |
| PWM 型： | 电压模式 |
| 输出数： | 6 |
| 频率 - 最大： | 275kHz |
| 占空比： | 66.7% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 包装： | 管件 |
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ISL6307
controller will execute 12.5mV changes six times per cycle
until VID and DAC are equal. It is for this reason that it is
important to carefully control the rate of VID stepping in 1-bit
increments.
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network
composed of R REF and C REF is required for an ISL6307
based voltage regulator. The selection of R REF is based on
the desired offset as detailed above in Output-Voltage Offset
Programming . The selection of C REF is based on the time
duration for 1 bit VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at 1
bit every T VID , the relationship between the time constant of
R REF and C REF network and T VID is given by Equation 13.
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6307 is guaranteed. Hysteresis between the rising
and falling thresholds assure that once enabled, the
ISL6307 will not inadvertently turn off unless the bias
voltage drops substantially (see Electrical
Specifications ).
2. The ISL6307 features an enable input (EN_PWR) for
power sequencing between the controller bias voltage
and another voltage rail. The enable comparator holds
the ISL6307 in shutdown until the voltage at EN_PWR
rises above 0.875V. The enable comparator has about
130mV of hysteresis to prevent bounce. It is important
that the driver ICs reach their POR level before the
ISL6307 becomes enabled. The schematic in Figure 10
demonstrates sequencing the ISL6307 with the ISL66xx
C REF R RE F = T VID
(EQ. 13)
family of Intersil MOSFET drivers, which require 12V
bias.
3. The voltage on EN_VTT must be higher than 0.875V to
Operation Initialization
Prior to converter initialization, proper conditions must exist
on the enable inputs and VCC. When the conditions are met,
the controller begins soft-start. Once the output voltage is
within the proper window of operation, VR_RDY asserts a
logic 1.
enable the controller. This pin is typically connected to the
output of VTT VR.
When all conditions above are satisfied, ISL6307 begins the
soft-start and ramps the output voltage to 1.1V first. After
remaining at 1.1V for some time, ISL6307 reads the VID
code at VID input pins. If the VID code is valid, ISL6307 will
regulate the output to the final VID setting. If the VID code is
ISL6307 INTERNAL CIRCUIT
EXTERNAL CIRCUIT
OFF code, ISL6307 will shut down. Cycling Vcc, EN_PWR
VCC
+ 12 V
or EN_VTT is needed to restart.
Soft-Start
POR
CIRCUIT
ENABLE
COMPARATOR
+
-
0.875V
10k ?
EN_PWR
91 0?
ISL6307 based VR has 4 periods during soft-start, as shown
in Figure 11. After Vcc, EN_VTT and EN_PWR reach their
POR and enable thresholds, The controller will have fixed
delay period TD1. After this delay period, the VR will begin
first soft-start ramp until the output voltage reaches 1.1V,
Vboot voltage. Then, the controller will regulate the VR
voltage at 1.1V for another fixed period, TD3. At the end of
TD3 period, ISL6307 will read the VID signals. If the VID
+
-
0.875V
EN_VTT
code is valid, ISL6307 will initiate the second soft-start ramp
until the voltage reaches the VID voltage minus offset
voltage.
The soft-start time is the sum of the 4 periods as shown in
the following equation.
SOFT-START
AND
T SS = TD1 + TD2 + TD3 + TD4
(EQ. 14)
FAULT LOGIC
FIGURE 10. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (EN) FUNCTION
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6307 is
released from shutdown mode.
22
TD1 is the fixed delay with typical value as 1.36ms. TD3 is
determined by the fixed 85μs plus the time to obtain valid
VID voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to valid the VID input is 500ns.
Therefore the minimum TD3 is about 86μs.
During TD2 and TD4, ISL6307 digitally controls the DAC
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator which
is defined by the resistor Rss from SS pin to GND. The 2
FN9224.0
March 9, 2006
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6307CRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6307IRZ | 功能描述:IC REG CTRLR BUCK PWM VM 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6307IRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6308ACRZ | 功能描述:IC CTRLR PWM BUCK 3PHASE 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6308ACRZR5609 | 制造商:Intersil Corporation 功能描述:PB-FREE DAC-LESS MULTI-PHASE PWM CONTR W/3-DRIVERS, HARD WI - Rail/Tube |
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