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参数资料
| 型号： | ISL6307CRZ |
| 厂商： | Intersil |
| 文件页数： | 30/34页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 48-QFN |
| 标准包装： | 43 |
| PWM 型： | 电压模式 |
| 输出数： | 6 |
| 频率 - 最大： | 275kHz |
| 占空比： | 66.7% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 包装： | 管件 |
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ISL6307
higher if desired. Choosing f HF to be lower than 10f 0 can
cause problems with too much phase shift below the system
bandwidth.
------------------- ≤ f 0 < ------------------------------
Case 2:
1 1
2 π LC 2 π C ( ESR )
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
V PP ( 2 π ) f 0 LC
R C = R FB --------------------------------------------
0.75 V
0.75V IN
C C = -------------------------------------------------------------
PP R FB LC
( 2 π ) 2 f 2 V
R 1 = R FB -----------------------------------------
0
2 2
IN
(EQ. 34
Equation 35, R FB is selected arbitrarily. The remaining
compensation components are then selected according to
Equation 35.
C ( ESR )
LC – C ( ESR )
C 1 = -----------------------------------------
C 2 = -------------------------------------------------------------------
( 2 π ) 0 HF LCR FB V PP
V PP ? 2 π ? f 0 f HF LCR FB
R C = ---------------------------------------------------------------------
? 2 π f
HF LC – 1 ?
?
?
0.75 V
a position available for C 2 , and be prepared to install a high-
frequency capacitor of between 22pF and 150pF in case any
leading-edge jitter problem is noted.
Once selected, the compensation values in Equation 34
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R C . Slowly increase the
value of R C while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
LC – C ( ESR )
R FB
0.75V IN
2 f f
2
? ?
IN
0.75V IN ? 2 π f
HF LC – 1 ?
C C = -------------------------------------------------------------------
C C will not need adjustment. Keep the value of C C from
Equation 34 unless some performance issue is noted.
COMPENSATION WITHOUT LOAD-LINE REGULATION
?
?
( 2 π ) 2 f 0 f HF LCR FB V PP
(EQ. 35)
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
resonant frequency and a zero at the ESR frequency. A
type III controller, as shown in Figure 21, provides the
necessary compensation.
C 2
In Equation 35, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and V PP is the peak-to-
peak sawtooth signal amplitude as described in Figure 7 and
Electrical Specifications .
R C
C C
COMP
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
C 1
FB
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
R 1
R FB
IDROOP
VDIFF
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter necessarily limits the
system transient response. The output capacitor must
supply or sink load current while the current in the output
inductors increases or decreases to meet the demand.
FIGURE 21. COMPENSATION CIRCUIT FOR ISL6307 BASED
CONVERTER WITHOUT LOAD-LINE
REGULATION
The first step is to choose the desired bandwidth, f 0 , of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than
1/3 of the switching frequency. The type-III compensator has
an extra high-frequency pole, f HF . This pole can be used for
added noise rejection or to assure adequate attenuation at
the error-amplifier high-order pole and zero frequencies. A
good general rule is to choose f HF = 10f 0 , but it can be
30
In high-speed converters, the output capacitor bank is
usually the most costly (and often the largest) part of the
circuit. Output filter design begins with minimizing the cost of
this part of the circuit. The critical load parameters in
choosing the output capacitors are the maximum size of the
load step, ? I; the load-current slew rate, di/dt; and the
maximum allowable output-voltage deviation under transient
loading, ? V MAX . Capacitors are characterized according to
their capacitance, ESR, and ESL (equivalent series
inductance).
FN9224.0
March 9, 2006
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| ISL6307CRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6307IRZ | 功能描述:IC REG CTRLR BUCK PWM VM 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6307IRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6308ACRZ | 功能描述:IC CTRLR PWM BUCK 3PHASE 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6308ACRZR5609 | 制造商:Intersil Corporation 功能描述:PB-FREE DAC-LESS MULTI-PHASE PWM CONTR W/3-DRIVERS, HARD WI - Rail/Tube |
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