参数资料
型号: ISL6308IRZ
厂商: Intersil
文件页数: 19/28页
文件大小: 0K
描述: IC CTRLR PWM 3PHASE BUCK 40-QFN
标准包装: 500
应用: 控制器,DDR
输入电压: 5 V ~ 12 V
输出数: 1
输出电压: 0.6 V ~ 2.3 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘
供应商设备封装: 40-QFN(6x6)
包装: 管件
ISL6308
through the upper MOSFET across V IN . The power
dissipated as a result is P UP,3 .
In Equations 20 and 21, P Qg_Q1 is the total upper gate drive
power loss and P Qg_Q2 is the total lower gate drive power
P UP , 3 = V IN ? Q rr ? F SW
(EQ. 18)
loss; the gate charge (Q G1 and Q G2 ) is defined at the
particular gate to source drive voltage PVCC in the
Finally, the resistive part of the upper MOSFET is given in
corresponding MOSFET data sheet; I Q is the driver total
I PP2
? I M ?
P UP , 4 ≈ r DS ( ON ) ? d ? ? ------ ? + ----------
Equation 19 as P UP,4 .
? N ? 12
2
(EQ. 19)
quiescent current with no load at both drive outputs; N Q1
and N Q2 are the number of upper and lower MOSFETs per
phase, respectively; N PHASE is the number of active
phases. The I Q* VCC product is the quiescent power of the
controller without capacitive load and is typically 75mW at
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
300kHz.
from Equations 16, 17, 18 and 19. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
PVCC
BOOT
C GD
D
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
R HI1
UGATE
G
C DS
Package Power Dissipation
R LO1
R G1
R GI1
C GS
Q1
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of three
drivers in the controller package, the total power dissipated
by all three drivers must be less than the maximum
allowable power dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
S
PHASE
FIGURE 15. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
D
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 6x6 QFN package is approximately 4W at
room temperature. See “Layout Considerations” on page 25
R HI2
R LO2
LGATE
G
R G2
C GD
R GI2
C GS
C DS
Q2
for thermal transfer improvement suggestions.
When designing the ISL6308 into an application, it is
recommended that the following calculation is used to
ensure safe operation at the desired frequency for the
selected MOSFETs. The total gate drive power losses,
P Qg_TOT , due to the gate charge of MOSFETs and the
integrated driver ’s internal circuitry and their corresponding
average driver current can be estimated with Equations 20
and 21, respectively.
S
FIGURE 16. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
the controller itself is the power dissipated in the upper drive
path resistance, P DR_UP , the lower drive path resistance,
P Qg_Q1 = --- ? Q G1 ? PVCC ? F SW ? N Q1 ? N PHASE
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q ? VCC
3
2
(EQ. 20)
P DR_UP , and in the boot strap diode, P BOOT . The rest of the
power will be dissipated by the external gate resistors (R G1
and R G2 ) and the internal gate resistors (R GI1 and R GI2 ) of
the MOSFETs. Figures 15 and 16 show the typical upper
and lower gate drives turn-on transition path. The total power
P Qg_Q2 = Q G2 ? PVCC ? F SW ? N Q2 ? N PHASE
(EQ. 21)
? 3 --- ? Q
G1 ? N Q1 + Q G2 ? N Q2 ?
I DR =
? 2
19
? ? N
PHASE ? F SW + I Q
FN9208.4
September 30, 2008
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