参数资料
| 型号： | ISL6308IRZ |
| 厂商： | Intersil |
| 文件页数： | 24/28页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 3PHASE BUCK 40-QFN |
| 标准包装： | 500 |
| 应用： | 控制器，DDR |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 2.3 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 供应商设备封装： | 40-QFN（6x6） |
| 包装： | 管件 |
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ISL6308
F Z1 F Z2
F P1
F P2
MODULATOR GAIN
COMPENSATION GAIN
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination
CLOSED LOOP GAIN
OPEN LOOP E/A GAIN
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
20 log ? -------- ?
OSC
0
R2
? R1 ?
d MAX ? V IN
20 log ---------------------------------
V
G CL
G FB
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor ac ripple current (see “Interleaving” on
LOG
F LC
F CE
F 0
G MOD
FREQUENCY
page 9 and Equation 2), a voltage develops across the bulk
capacitor ESR equal to I C,PP (ESR). Thus, once the output
capacitors are selected, the maximum allowable ripple
FIGURE 22. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
voltage, V PP(MAX) , determines the lower limit on the
inductance.
IN – N ? V OUT ? V OUT
? V ?
L ≥ ( ESR ) ? --------------------------------------------------------------------
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
? ?
F SW ? V IN ? V PP ( MAX )
(EQ. 40)
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter limits the system
transient response. The output capacitors must supply or
sink load current while the current in the output inductors
increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is
usually the most costly (and often the largest) part of the
circuit. Output filter design begins with minimizing the cost of
this part of the circuit. The critical load parameters in
choosing the output capacitors are the maximum size of the
load step, Δ I, the load-current slew rate, di/dt, and the
maximum allowable output-voltage deviation under transient
loading, Δ V MAX . Capacitors are characterized according to
their capacitance, ESR, and ESL (equivalent series
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
Δ V MAX . This places an upper limit on inductance.
Equation 41 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 42
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
L ≤ ---------------------------------- ? Δ V MAX – ( Δ I ? ESR ) ? ? V IN – V O ?
( Δ I ) 2
L ≤ --------------------------------- ? Δ V MAX – ( Δ I ? ESR )
inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
( 1.25 ) ? N ? C
2 ? N ? C ? V O
( Δ I ) 2
? ?
(EQ. 42)
(EQ. 41)
(EQ. 39)
Δ V ≈ ( ESL ) ? ----- + ( ESR ) ? Δ I
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
as follows:
di
dt
The filter capacitor must have sufficiently low ESL and ESR
so that Δ V < Δ V MAX .
24
Switching Frequency
There are a number of variables to consider when choosing
the switching frequency, as there are considerable effects on
the upper MOSFET loss calculation. These effects are
outlined in “MOSFETs” on page 18, and they establish the
upper limit for the switching frequency. The lower limit is
established by the requirement for fast transient response
and small output-voltage ripple as outlined in “Output Filter
Design” on page 24. Choose the lowest switching frequency
that allows the regulator to meet the transient-response
requirements.
FN9208.4
September 30, 2008
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相关代理商/技术参数 |
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| ISL6308IRZ-T | 功能描述:电压模式 PWM 控制器 DAC-LESS MULTI-PHS PWM CNTRLR W/3-DRVRS RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| ISL6308IRZ-TR5453 | 制造商:Intersil Corporation 功能描述:STD. ISL6308IRZ-T WITH GOLD BOND WIRE ONLY - Tape and Reel |
| ISL6310CRZ | 功能描述:电压模式 PWM 控制器 W/ANNEAL 2-PH PWM CNTRLR W/2-DRVRS RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| ISL6310CRZ-T | 功能描述:电压模式 PWM 控制器 W/ANNEAL 2-PH PWM CNTRLR W/2-DRVRS RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| ISL6310EVAL1Z | 功能描述:EVALUATION BOARD FOR ISL6310 RoHS:是 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:True Shutdown™ 主要目的:DC/DC，步升 输出及类型:1，非隔离 功率 - 输出:- 输出电压:- 电流 - 输出:1A 输入电压:2.5 V ~ 5.5 V 稳压器拓扑结构:升压 频率 - 开关:3MHz 板类型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
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