参数资料
| 型号： | ISL6310CRZ-T |
| 厂商： | Intersil |
| 文件页数： | 15/27页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 2PHASE BUCK 32-QFN |
| 标准包装： | 6,000 |
| 应用： | 控制器，DDR |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 2.3 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 带卷 (TR) |
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ISL6310
ISL6310 INTERNAL CIRCUIT
EXTERNAL CIRCUIT
VCC
A 100mV offset exists on the remote-sense amplifier at the
beginning of soft-start and ramps to zero during the first 640
cycles of soft-start (704 cycles following enable). This
prevents the large inrush current that would otherwise occur
POR
PVCC
+ 12 V
should the output voltage start out with a slight negative
bias.
During the first 640 cycles of soft-start (704 cycles following
CIRCUIT
ENABLE
COMPARATOR
+
-
0.66V
10.7k Ω
ENLL
1.40k Ω
enable) the DAC voltage increments the reference in 25mV
steps. The remainder of soft-start sees the DAC ramping
with 12.5mV steps.
The ISL6310 also has the ability to start up into a
pre-charged output as shown in Figure 12, without causing
any unnecessary disturbance. The FB pin is monitored
during soft-start, and should it be higher than the equivalent
internal ramping reference voltage, the output drives hold
SOFT-START
AND
FAULT LOGIC
FIGURE 11. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (ENLL) FUNCTION
2. The voltage on ENLL must be above 0.66V. The EN input
allows for power sequencing between the controller bias
voltage and another voltage rail. The enable comparator
holds the ISL6310 in shutdown until the voltage at ENLL
rises above 0.66V. The enable comparator has 100mV of
hysteresis to prevent bounce.
3. The driver bias voltage applied at the PVCC pins must
reach the internal power-on reset (POR) rising threshold.
In order for the ISL6310 to begin operation, PVCC is the
only pin that is required to have a voltage applied that
exceeds POR. Hysteresis between the rising and falling
both MOSFETs off. Once the internal ramping reference
exceeds the FB pin potential, the output drives are enabled,
allowing the output to ramp from the pre-charged level to the
final level dictated by the reference setting. Should the
output be pre-charged to a level exceeding the reference
setting, the output drives are enabled at the end of the
soft-start period, leading to an abrupt correction in the output
voltage down to the “reference set” level.
OUTPUT PRECHARGED
ABOVE DAC LEVEL
OUTPUT PRECHARGED
BELOW DAC LEVEL
thresholds assure that once enabled, the ISL6310 will not
inadvertently turn off unless the PVCC bias voltage drops
When each of these conditions is true, the controller
immediately begins the soft-start sequence.
Soft-Start
During soft-start, the DAC voltage ramps linearly from zero
GND>
GND>
T1 T2
T3
V OUT (0.5V/DIV)
ENLL (5V/DIV)
to the programmed level. The PWM signals remain in the
high-impedance state until the controller detects that the
ramping DAC level has reached the output-voltage level.
This protects the system against the large, negative inductor
currents that would otherwise occur when starting with a
pre-existing charge on the output as the controller attempted
to regulate to zero volts at the beginning of the soft-start
cycle. The Output soft-start time, t SS , begins with a delay
period equal to 64 switching cycles after the ENLL has
exceeded its POR level, followed by a linear ramp with a rate
determined by the switching period, 1/F SW .
FIGURE 12. SOFT-START WAVEFORMS FOR ISL6310-BASED
MULTI-PHASE CONVERTER
Fault Monitoring and Protection
The ISL6310 actively monitors output voltage and current to
detect fault conditions. Fault monitors trigger protective
measures to prevent damage to the sensitive load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 13
outlines the interaction between the fault monitors and the
power good signal.
t SS = --------------------------------------------
64 + DAC ? 1280
F SW
(EQ. 12)
For example, a regulator with 450kHz switching frequency
having REF voltage set to 1.2V has t SS equal to 3.55ms.
15
FN9209.4
August 7, 2008
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相关代理商/技术参数 |
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| ISL6310EVAL1Z | 功能描述:EVALUATION BOARD FOR ISL6310 RoHS:是 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:True Shutdown™ 主要目的:DC/DC，步升 输出及类型:1，非隔离 功率 - 输出:- 输出电压:- 电流 - 输出:1A 输入电压:2.5 V ~ 5.5 V 稳压器拓扑结构:升压 频率 - 开关:3MHz 板类型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
| ISL6310IRZ | 功能描述:电压模式 PWM 控制器 W/ANNEAL 2-PH PWM CNTROL W/2-DRVRS RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| ISL6310IRZ-T | 功能描述:电压模式 PWM 控制器 W/ANNEAL 2-PH PWM CNTROL W/2-DRVRS RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| ISL6312ACRZ | 功能描述:IC CTRLR PWM 4PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
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