参数资料
型号: ISL6310CRZ-T
厂商: Intersil
文件页数: 9/27页
文件大小: 0K
描述: IC CTRLR PWM 2PHASE BUCK 32-QFN
标准包装: 6,000
应用: 控制器,DDR
输入电压: 5 V ~ 12 V
输出数: 1
输出电压: 0.6 V ~ 2.3 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN(5x5)
包装: 带卷 (TR)
ISL6310
PGOOD (Pin 28)
PGOOD is used as an indication of the end of soft-start. It is
an open-drain logic output that is low impedance until the
soft-start is completed and V OUT is equal to the VID setting.
Once in normal operation, PGOOD indicates whether the
output voltage is within specified overvoltage and
undervoltage limits. If the output voltage exceeds these limits
or a reset event occurs (such as an overcurrent event),
PGOOD becomes high impedance again. The potential at this
pin should not exceed that of the potential at VCC pin by more
than a typical forward diode drop at any time
OVP (Pin 22)
Overvoltage protection pin. This pin pulls to VCC when an
overvoltage condition is detected. Connect this pin to the
gate of an SCR or MOSFET tied across V IN and ground to
prevent damage to a load device.
Operation
Multi-Phase Power Conversion
I L1 + I L2
I L2
PWM2
I L1
PWM1
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS
FOR 2-PHASE CONVERTER
To understand the reduction of ripple current amplitude in the
multi-phase circuit, examine Equation 1, which represents
an individual channel peak-to-peak inductor current.
( V IN – V OUT ) ? V OUT
L ? F SW ? V IN
Modern low voltage DC/DC converter load current profiles
have changed to the point that the advantages of multi-phase
power conversion are impossible to ignore. The technical
I PP = ----------------------------------------------------------
(EQ. 1)
challenges associated with producing a single-phase
converter that is both cost-effective and thermally viable have
forced a change to the cost-saving approach of multi-phase.
The ISL6310 controller helps simplify implementation by
integrating vital functions and requiring minimal external
components. The “Block Diagram” on page 3 provides a top
level view of multi-phase power conversion using the ISL6310
controller.
Interleaving
The switching of each channel in an ISL6310-based
converter is timed to be symmetrically out-of-phase with the
other channel. As a result, the two-phase converter has a
combined ripple frequency twice the frequency of one of its
phases. In addition, the peak-to-peak amplitude of the
combined inductor currents is proportionately reduced
In Equation 1, V IN and V OUT are the input and output
voltages respectively, L is the single-channel inductor value,
and F SW is the switching frequency.
The output capacitors conduct the ripple component of the
inductor current. In the case of multi-phase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 1 to the
expression for the peak-to-peak current after the summation
of N symmetrically phase-shifted inductor currents in
Equation 2. Peak-to-peak ripple current decreases by an
amount proportional to the number of channels. Output
voltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple
current. Reducing the inductor ripple current allows the
designer to use fewer or less costly output capacitors.
L ? F SW ? V
(Equations 1 and 2).
Increased ripple frequency and lower ripple amplitude
generally translate to lower per-channel inductance and
( V IN – N ? V OUT ) ? V OUT
I C , PP = --------------------------------------------------------------------
IN
(EQ. 2)
lower total output capacitance for a given set of performance
specifications. Figure 1 illustrates the additive effect on
output ripple frequency. The two channel currents (I L1 and
I L2 ), combine to form the AC ripple current and the DC load
current. The ripple component has two times the ripple
frequency of each individual channel current.
9
Another benefit of interleaving is to reduce input ripple
current. Input capacitance is determined in part by the
maximum input ripple current. Multi-phase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 2 illustrates input
currents from a two-phase converter combining to reduce
the total input ripple current.
FN9209.4
August 7, 2008
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