参数资料
| 型号： | ISL6310CRZ-T |
| 厂商： | Intersil |
| 文件页数： | 22/27页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 2PHASE BUCK 32-QFN |
| 标准包装： | 6,000 |
| 应用： | 控制器，DDR |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 2.3 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 带卷 (TR) |
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ISL6310
and C 3 ) in Figures 20 and 21. Use the following guidelines for
3. Calculate C 2 such that F P1 is placed at F CE .
2 π ? R 2 ? C 1 ? F CE – 1
locating the poles and zeros of the compensation network:
1. Select a value for R 1 (1k Ω to 5k Ω , typically). Calculate
C 1
C 2 = --------------------------------------------------------
(EQ. 32)
d MAX ? V IN ? F LC
R 3 = ----------------------
F SW
------------ – 1
F LC
C 3 = -------------------------------------------------
value for R 2 for desired converter bandwidth (F 0 ). If
setting the output voltage to be equal to the reference set
voltage as shown in Figure 22, the design procedure can
be followed as presented. However, when setting the
output voltage via a resistor divider placed at the input of
the differential amplifier (as shown in Figure 6), in order
to compensate for the attenuation introduced by the
resistor divider, the obtained R 2 value needs be
multiplied by a factor of (R P1 + R S1 )/R P1 . The remainder
of the calculations remain unchanged, as long as the
compensated R 2 value is used.
V OSC ? R 1 ? F 0 (EQ. 30)
R 2 = ---------------------------------------------
C 2
4. Calculate R 3 such that F Z2 is placed at F LC . Calculate C 3
such that F P2 is placed below F SW (typically, 0.5 to 1.0
times F SW ). F SW represents the per-channel switching
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F P2 lower in frequency
helps reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at the
COMP pin and minimizing resultant duty cycle jitter.
R 1
(EQ. 33)
1
2 π ? R 3 ? 0.7 ? F SW
It is recommended that a mathematical model is used to plot
the loop response. Check the loop gain against the error
amplifier ’s open-loop gain. Verify phase margin results and
COMP
R 2
C 1
R 3
C 3
adjust as necessary. The following equations describe the
frequency response of the modulator (G MOD ), feedback
-
compensation (G FB ) and closed-loop response (G CL ):
G MOD ( f ) = ------------------------------ ? -----------------------------------------------------------------------------------------------------------
V OSC
1 + s ( f ) ? ( ESR + DCR ) ? C + s ( f ) ? L ? C
G FB ( f ) = ---------------------------------------------------- ?
s ( f ) ? R 1 ? ( C 1 + C 2 )
1 + s ( f ) ? ( R 1 + R 3 ) ? C 3
( 1 + s ( f ) ? R 3 ? C 3 ) ? ? 1 + s ( f ) ? R 2 ? ? ? ?
? ? C 1 ? C 2 ? ?
E/A
+
VREF
-
+
FB
VDIFF
RGND
VSEN
R 1
d MAX ? V IN 1 + s ( f ) ? ESR ? C
2
1 + s ( f ) ? R 2 ? C 1
(EQ. 34)
-------------------------------------------------------------------------------------------------------------------------
---------------------
? ? C 1 + C 2 ? ?
OSCILLATOR
V OUT
G CL ( f ) = G MOD ( f ) ? G FB ( f )
where , s ( f ) = 2 π ? f ? j
V IN
PWM
V OSC
COMPENSATION BREAK FREQUENCY EQUATIONS
F Z1 = -------------------------------
F Z2 = -------------------------------------------------
F P1 = ---------------------------------------------
2 π ? R 2 ? ---------------------
CIRCUIT
HALF-BRIDGE
DRIVE
UGATE
PHASE
LGATE
L
DCR
C
ESR
1
2 π ? R 2 ? C 1
1
2 π ? ( R 1 + R 3 ) ? C 3
1
C 1 ? C 2
C 1 + C 2
(EQ. 35)
(EQ. 36)
(EQ. 37)
F P2 = -------------------------------
ISL6310 EXTERNAL CIRCUIT
FIGURE 22. VOLTAGE-MODE BUCK CONVERTER
1
2 π ? R 3 ? C 3
(EQ. 38)
COMPENSATION DESIGN
2. Calculate C 1 such that F Z1 is placed at a fraction of the F LC ,
at 0.1 to 0.75 of F LC (to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F CE /F LC , the lower the F Z1
frequency (to maximize phase boost at F LC ).
Figure 23 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
C 1 = -----------------------------------------------
1
2 π ? R 2 ? 0.5 ? F LC
22
(EQ. 31)
compensation gain at F P2 against the capabilities of the error
amplifier. The closed loop gain, G CL , is constructed on the
log-log graph of Figure 23 by adding the modulator gain,
G MOD (in dB), to the feedback compensation gain, G FB (in
FN9209.4
August 7, 2008
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