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参数资料
| 型号： | ISL6310EVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 12/27页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD FOR ISL6310 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 1.5V |
| 电流 - 输出： | 60A |
| 输入电压： | 5 ~ 12 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 400kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ISL6310 |
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ISL6310
Voltage Regulation
In order to regulate the output voltage to a specified level, the
ISL6310 uses the integrating compensation network shown in
Figure 6. This compensation network insures that the steady
state error in the output voltage is limited only to the error in
the reference voltage (output of the DAC or the external
voltage reference) and offset errors in the OFS current
source, remote sense and error amplifiers. Intersil specifies
The output of the error amplifier, V COMP , is compared to the
sawtooth waveform to generate the PWM signals. The PWM
signals control the timing of the Internal MOSFET drivers
and regulate the converter output so that the voltage at FB is
equal to the voltage at REF. This will regulate the output
voltage to be equal to Equation 5. The internal and external
circuitry that controls voltage regulation is illustrated in
Figure 6.
the guaranteed tolerance of the ISL6310 to include the
combined tolerances of each of these elements, except when
an external reference or voltage divider is used, then the
tolerances of these components has to be taken into account.
V OUT = V REF ± V OFS – V DROOP
Load Line (Droop) Regulation
(EQ. 5)
EXTERNAL CIRCUIT
ISL6310 INTERNAL CIRCUIT
In some high current applications, a requirement on a
R 2
C 1
COMP
DAC
VID DAC
precisely controlled output impedance is imposed. This
dependence of output voltage on load current is often
termed “droop” or “load line” regulation.
The Droop is an optional feature in the ISL6310. It can be
REF
enabled by connecting ICOMP pin to DROOP pin, as shown
C REF
FB
+
-
in Figure 6. To disable it, connect the DROOP pin to IREF
pin.
R 1
+
V OFS
-
VDIFF
I OFS
V COMP
ERROR AMPLIFIER
As shown in Figure 6, a voltage, V DROOP , proportional to the
total current in all active channels, I OUT , feeds into the
differential remote-sense amplifier. The resulting voltage at
the output of the remote-sense amplifier is the sum of the
R S1
VSEN
output voltage and the droop voltage. As Equation 5 shows,
+
V OUT
-
R P1
RGND
+
+
-
feeding this voltage into the compensation network causes
the regulator to adjust the output voltage so that it’s equal to
the reference voltage minus the droop voltage.
The droop voltage, V DROOP , is created by sensing the
-
V DROOP
+
DROOP
IREF
-
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
current through the output inductors. This is accomplished
by using a continuous DCR current sensing method.
Inductor windings have a characteristic distributed
resistance or DCR (Direct Current Resistance). For
C SUM
ICOMP
ISUM
+
ISENSE
AMP
-
simplicity, the inductor DCR is considered as a separate
lumped quantity, as shown in Figure 7. The channel current,
I L , flowing through the inductor, passes through the DCR.
Equation 6 shows the s-domain equivalent voltage, V L ,
across the inductor.
FIGURE 6. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
V L ( s ) = I L ? ( s ? L + DCR )
(EQ. 6)
s ? L
? ------------- + 1 ?
( s ? R COMP ? C COMP + 1 )
V DROOP ( s ) = -------------------------------------------------------------------------- ? ----------------------- ? ( I L1 + I L2 ) ? DCR
The ISL6310 incorporates an internal differential remote
sense amplifier in the feedback path. The amplifier removes
the voltage error encountered when measuring the output
voltage relative to the controller ground reference point,
resulting in a more accurate means of sensing output voltage.
Connect the load’s output sense pins to the non-inverting
input, VSEN, and inverting input, RGND, of the remote sense
amplifier. The droop voltage, V DROOP , also feeds into the
remote sense amplifier. The remote sense output, V DIFF , is
therefore equal to the sum of the output voltage, V OUT , and
the droop voltage. V DIFF is connected to the inverting input of
the error amplifier through an external resistor.
12
The inductor DCR is important because the voltage dropped
across it is proportional to the channel current. By using a
simple R-C network and a current sense amplifier, as shown
in Figure 7, the voltage drop across all of the inductors DCRs
can be extracted. The output of the current sense amplifier,
V DROOP , can be shown to be proportional to the channel
currents I L1 and I L2 , shown in Equation 7.
(EQ. 7)
? DCR ? R COMP
RS
FN9209.4
August 7, 2008
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相关代理商/技术参数 |
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| ISL6310IRZ | 功能描述:电压模式 PWM 控制器 W/ANNEAL 2-PH PWM CNTROL W/2-DRVRS RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| ISL6310IRZ-T | 功能描述:电压模式 PWM 控制器 W/ANNEAL 2-PH PWM CNTROL W/2-DRVRS RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| ISL6312ACRZ | 功能描述:IC CTRLR PWM 4PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
| ISL6312ACRZ-T | 功能描述:IC CTRLR PWM 4PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
| ISL6312AIRZ | 功能描述:IC CTRLR PWM 4PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
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