参数资料
| 型号： | ISL6313BIRZ-T |
| 厂商： | Intersil |
| 文件页数： | 11/33页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM BUCK 2PHASE 36-TQFN |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 4,000 |
| 应用： | 控制器，Intel VR11，AMD CPU |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 1.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-WFQFN 裸露焊盘 |
| 供应商设备封装： | 36-TQFN 裸露焊盘（6x6） |
| 包装： | 带卷 (TR) |
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ISL6313B
The output capacitors conduct the ripple component of the
inductor current. In the case of multi-phase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 1 to the
expression for the peak-to-peak current after the summation
of N symmetrically phase-shifted inductor currents in
Equation 2. Peak-to-peak ripple current decreases by an
amount proportional to the number of channels. Output
voltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple
current. Reducing the inductor ripple current allows the
designer to use fewer or less costly output capacitors.
frequency set by the resistor connected to the FS pin. The
advantage of Intersil’s proprietary Active Pulse Positioning
(APP) modulator is that the PWM signal has the ability to
turn on at any point during this PWM time interval, and turn
off immediately after the PWM signal has transitioned high.
This is important because is allows the controller to quickly
respond to output voltage drops associated with current load
spikes, while avoiding the ring back affects associated with
other modulation schemes.
The PWM output state is driven by the position of the error
amplifier output signal, V COMP minus the current correction
L ? f S ? V
( V IN – N ? V OUT ) ? V OUT
I C ( PP ) = --------------------------------------------------------------------
IN
(EQ. 2)
signal relative to the proprietary modulator ramp waveform
as illustrated in Figure 4. At the beginning of each PWM time
interval, this modified V COMP signal is compared to the
Another benefit of interleaving is to reduce input ripple
current. Input capacitance is determined in part by the
maximum input ripple current. Multiphase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 2 illustrates input
currents from a three-phase converter combining to reduce
the total input ripple current.
The converter depicted in Figure 2 delivers 1.5V to a 36A load
from a 12V input. The RMS input capacitor current is 5.9A.
Compare this to a single-phase converter also stepping down
12V to 1.5V at 36A. The single-phase converter has
11.9A RMS input capacitor current. The single-phase converter
must use an input capacitor bank with twice the RMS current
capacity as the equivalent three-phase converter.
INPUT-CAPACITOR CURRENT, 10A/DIV
internal modulator waveform. As long as the modified
V COMP voltage is lower then the modulator waveform
voltage, the PWM signal is commanded low. The internal
MOSFET driver detects the low state of the PWM signal and
turns off the upper MOSFET and turns on the lower
synchronous MOSFET. When the modified V COMP voltage
crosses the modulator ramp, the PWM output transitions
high, turning off the synchronous MOSFET and turning on
the upper MOSFET. The PWM signal will remain high until
the modified V COMP voltage crosses the modulator ramp
again. When this occurs the PWM signal will transition low
again.
During each PWM time interval the PWM signal can only
transition high once. Once PWM transitions high it can not
transition high again until the beginning of the next PWM
time interval. This prevents the occurrence of double PWM
pulses occurring during a single period.
CHANNEL 3
EXTERNAL CIRCUIT
ISL6313B INTERNAL CIRCUIT
INPUT CURRENT
APA
CHANNEL 2
INPUT CURRENT
C APA
R APA
V APA,TRIP
100μA
+
APA
-
TO APA
CHANNEL 1
INPUT CURRENT
1μs/DIV
COMP
LOW
PASS
FILTER
ERROR
AMPLIFIER
CIRCUITRY
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-
CAPACITOR RMS CURRENT FOR 3-PHASE
CONVERTER
FIGURE 3. ADAPTIVE PHASE ALIGNMENT DETECTION
Active Pulse Positioning (APP) Modulated PWM
Operation
The ISL6313B uses a proprietary Active Pulse Positioning
(APP) modulation scheme to control the internal PWM
signals that command each channel’s driver to turn their
upper and lower MOSFETs on and off. The time interval in
which a PWM signal can occur is generated by an internal
clock, whose cycle time is the inverse of the switching
11
Adaptive Phase Alignment (APA)
To further improve the transient response, the ISL6313B
also implements Intersil’s proprietary Adaptive Phase
Alignment (APA) technique, which turns on all of the
channels together at the same time during large current step
transient events. As Figure 3 shows, the APA circuitry works
by monitoring the voltage on the APA pin and comparing it to
FN6809.0
November 6, 2008
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| ISL6313CRZ | 制造商:Intersil Corporation 功能描述:TWO-PHASE BUCK PWM CNTRLR W/ INTEGRATED MOSFET DRVRS FOR INT - Rail/Tube 制造商:Intersil Corporation 功能描述:Switching Controllers 2-PH PWM CNTRLR W/2 INTEGRTD DRVRS 36LD |
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