参数资料
| 型号： | ISL6313BIRZ-T |
| 厂商： | Intersil |
| 文件页数： | 13/33页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM BUCK 2PHASE 36-TQFN |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 4,000 |
| 应用： | 控制器，Intel VR11，AMD CPU |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 1.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-WFQFN 裸露焊盘 |
| 供应商设备封装： | 36-TQFN 裸露焊盘（6x6） |
| 包装： | 带卷 (TR) |
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ISL6313B
I SEN = I L ? ------------------
V IN
I
L
DCR
R ISEN
(EQ. 6)
MOSFET
DRIVER
UGATE
LGATE
L
DCR
INDUCTOR
V L (s)
V OUT
C OUT
The effective internal R ISEN resistance is important to the
current sensing process because it sets the gain of the load
line regulation loop as well as the gain of the channel-current
balance loop and the overcurrent trip level. The effective
V C (s)
internal R ISEN resistance is user programmable and is set
I n
ISL6313B INTERNAL
CIRCUIT
R 1
C 1
through use of the RSET pin. Placing a single resistor, R SET ,
from the RSET pin to the VCC pin programs the effective
internal R ISEN resistance according to Equation 7 below. It is
SENSE
important to note that the R SET resistance value must be
between 20k Ω and 80k Ω for Equation 7 to be valid.
R ISEN = ---------- ? R SET
I SEN
+
-
V C (s)
R ISEN
ISEN-
ISEN+
RSET
3
400
*Note: R SET must be between 20k Ω and 80k Ω
Output Voltage Setting
(EQ. 7)
R SET
VCC
The ISL6313B uses a digital to analog converter (DAC) to
generate a reference voltage based on the logic signals at
FIGURE 6. INDUCTOR DCR CURRENT SENSING
CONFIGURATION
Inductor windings have a characteristic distributed
resistance or DCR (Direct Current Resistance). For
simplicity, the inductor DCR is considered as a separate
lumped quantity, as shown in Figure 6. The channel current
I L , flowing through the inductor, passes through the DCR.
Equation 4 shows the s-domain equivalent voltage, V L ,
across the inductor.
the VID pins. The DAC decodes the logic signals into one of
the discrete voltages shown in Tables 2, 3 or 4. In the Intel
VR11 mode of operation, each VID pin is pulled up to an
internal 1.2V voltage by a weak current source (40μA),
which decreases to 0A as the voltage at the VID pin varies
from 0 to the internal 1.2V pull-up voltage. In AMD modes of
operation the VID pins are pulled low by a week 20μA
current source. External pull-up resistors or active-high
output stages can augment the pull-up current sources, up to
a voltage of 5V.
The ISL6313B accommodates three different DAC ranges:
V L ( s ) = I L ? ( s ? L + DCR )
(EQ. 4)
.
Intel VR11, AMD K8/K9 5-bit, and AMD 6-bit. The state of
A simple R-C network across the inductor (R 1 and C)
extracts the DCR voltage, as shown in Figure 6. The voltage
across the sense capacitor, V C , can be shown to be
proportional to the channel current I L , shown in Equation 5.
the SS and VID7 pins decide which DAC version is active.
Refer to Table 1 for a description of how to select the desired
DAC version.
TABLE 1. ISL6313B DAC SELECT TABLE
? ------------- + 1 ?
V C ( s ) = ----------------------------------------- ? DCR ? I L
s ? L
? DCR ?
( s ? R 1 ? C 1 + 1 )
(EQ. 5)
DAC VERSION
INTEL VR11
SS PIN
R SS resistor tied to GND
VID7 PIN
-
If the R 1 -C 1 network components are selected such that
their time constant matches the inductor L/DCR time
AMD 5-BIT
AMD 6-BIT
R SS resistor tied to VCC
R SS resistor tied to VCC
high
low
constant, then V C is equal to the voltage drop across the
DCR.
TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES
The capacitor voltage V C , is then replicated across the
effective internal sense resistance R ISEN . This develops a
current through R ISEN which is proportional to the inductor
current. This current, I SEN , is continuously sensed and is
then used by the controller for load-line regulation, channel-
current balancing, and overcurrent detection and limiting.
Equation 6 shows that the proportion between the channel
current, I L , and the sensed current, I SEN , is driven by the
value of the effective sense resistance, R ISEN , and the DCR
of the inductor.
VID7
0
0
0
0
0
0
0
VID6
0
0
0
0
0
0
0
VID5
0
0
0
0
0
0
0
VID4
0
0
0
0
0
0
0
VID3
0
0
0
0
0
0
0
VID2
0
0
0
0
1
1
1
VID1
0
0
1
1
0
0
1
VID0
0
1
0
1
0
1
0
VDAC
OFF
OFF
1.60000
1.59375
1.58750
1.58125
1.57500
13
FN6809.0
November 6, 2008
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