参数资料
| 型号： | ISL6315IRZ |
| 厂商： | Intersil |
| 文件页数： | 16/20页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 24-QFN |
| 标准包装： | 75 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 255kHz |
| 占空比： | 67% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 包装： | 管件 |
ISL6315
different MOSFETs and different switching frequencies until
converging upon the best solution.
equation can be used to determine a lower limit on the
output inductance.
( V IN – 2 ? V OUT ) ? V OUT
f S ? V IN ? V P-P ( MAX )
OUTPUT FILTER DESIGN
The output inductors and the output capacitor bank together
form a low-pass filter responsible for smoothing the square
L ≥ ESR ? -----------------------------------------------------------------
(EQ. 22)
wave voltage at the phase nodes. Additionally, the output
capacitors must also provide the energy required by a fast
transient load during the short interval of time required by the
controller and power train to respond. Because it has a low
bandwidth compared to the switching frequency, the output
filter limits the system transient response leaving the output
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
Δ V MAX . This places an upper limit on inductance.
L ≤ -------------------------------- ? ( Δ V MAX – Δ I ? ESR )
( Δ I )
capacitor bank to supply the load current or sink the inductor
currents, all while the current in the output inductors
increases or decreases to meet the load demand.
4 ? C ? V OUT
2
(EQ. 23)
In high-speed converters, the output capacitor bank is
amongst the costlier (and often the physically largest) parts
of the circuit. Output filter design begins with consideration
of the critical load parameters: maximum size of the load
While the previous equation addresses the leading edge, the
following equation gives the upper limit on L for cases where
the trailing edge of the current transient causes a greater
output voltage deviation than the leading edge.
L ≤ ----------------- ? ( Δ V MAX – Δ I ? ESR ) ? ( V IN – V O )
( Δ I )
step, Δ I, the load-current slew rate, di/dt, and the maximum
allowable output voltage deviation under transient loading,
Δ V MAX . Capacitors are characterized according to their
2.5 ? C
2
(EQ. 24)
capacitance, ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output-
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates according to
the following equation:
Normally, the trailing edge dictates the selection of L, since
duty cycles are usually less than 50%. Nevertheless, both
inequalities should be evaluated, and L should be selected
based on the lower of the two results. In all equations in this
paragraph, L is the per-channel inductance and C is the total
output bulk capacitance.
LAYOUT CONSIDERATIONS
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit
Δ V ≈ ( ESL ) ----- + ( ESR ) Δ I
di
dt
(EQ. 21)
and lead to device overvoltage stress. Careful component
layout and printed circuit design minimizes the voltage
spikes in the converter. Consider, as an example, the turnoff
The filter capacitor must have sufficiently low ESL and ESR
so that Δ V < Δ V MAX .
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors is also responsible for the
majority of the output-voltage ripple. As the bulk capacitors
sink and source the inductor AC ripple current, a voltage
develops across the bulk-capacitor ESR equal to I P-P . Thus,
once the output capacitors are selected and a maximum
allowable ripple voltage, V P-P(MAX) , is determined from an
analysis of the available output voltage budget, the following
16
transition of the upper PWM MOSFET. Prior to turnoff, the
upper MOSFET was carrying channel current. During the
turnoff, current stops flowing in the upper MOSFET and is
picked up by the lower MOSFET. Any inductance in the
switched current path generates a large voltage spike during
the switching interval. Careful component selection, tight
layout of the critical components, and short, wide circuit
traces minimize the magnitude of voltage spikes.
There are two sets of critical components in a DC/DC
converter using a ISL6315 controller. The power
components are the most critical because they switch large
amounts of energy. Next are small signal components that
connect to sensitive nodes or supply critical bypassing
current and signal coupling.
Note that as the ISL6315 does not allow external adjustment
of the channel-to-channel current balancing (current
information is multiplexed across a single R ISEN resistor), it
FN9222.1
July 18, 2007
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| ISL6315IRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 24-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6316CRZ | 功能描述:软开关 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR COM RoHS:否 制造商:Fairchild Semiconductor 输出端数量: 输出电流: 开关频率: 工作电源电压:30 V 电源电流: 最大工作温度:+ 105 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Reel |
| ISL6316CRZ-T | 功能描述:软开关 PWM 控制器 W/ANNEAL ISL6306 4-PHS VR11 CNTRLRCOM RoHS:否 制造商:Fairchild Semiconductor 输出端数量: 输出电流: 开关频率: 工作电源电压:30 V 电源电流: 最大工作温度:+ 105 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Reel |
| ISL6316IRZ | 功能描述:软开关 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR INDUSTRIAL RoHS:否 制造商:Fairchild Semiconductor 输出端数量: 输出电流: 开关频率: 工作电源电压:30 V 电源电流: 最大工作温度:+ 105 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Reel |
| ISL6316IRZ-T | 功能描述:软开关 PWM 控制器 W/ANNEAL ISL6306 CNTRLR INDUSTRIAL RoHS:否 制造商:Fairchild Semiconductor 输出端数量: 输出电流: 开关频率: 工作电源电压:30 V 电源电流: 最大工作温度:+ 105 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Reel |
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