参数资料
型号: ISL6315IRZ
厂商: Intersil
文件页数: 7/20页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 24-QFN
标准包装: 75
PWM 型: 电压模式
输出数: 1
频率 - 最大: 255kHz
占空比: 67%
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 24-VFQFN 裸露焊盘
包装: 管件
ISL6315
Operation
The ISL6315 employs simple voltage-mode control. Figure 1
shows a simplified diagram of the voltage regulation and
current balance loops. Voltage feedback is used to precisely
regulate the output voltage, while current feedback tightly
controls the individual channel currents, I L1 and I L2 , and
trips the OC protection, if so necessary.
VOLTAGE LOOP
Feedback from the output voltage is applied via resistor R1
to the inverting input of the Error Amplifier. This signal can
drive the Error Amplifier output either high or low, depending
upon the output voltage. Low output voltage makes the
amplifier output move towards a higher output voltage level.
Amplifier output voltage is applied to the positive inputs of
the PWM Circuit comparators via the channel current
correction summing networks. Out-of-phase sawtooth
signals are applied to the two PWM comparators inverting
inputs. Increasing Error Amplifier voltage results in increased
Comparator output duty cycle. This increased duty cycle
signal is passed through the output drivers with no phase
reversal to drive the external upper MOSFETs. Increased
duty cycle or ON time for the upper MOSFET transistors
results in increased output voltage to compensate for the low
output voltage sensed.
CHANNEL BALANCE CURRENT LOOP
The current balance control loop works in a similar fashion to
the voltage control loop, but with current control information
applied individually to each channel’s PWM circuit. The
information used for this control is the voltage that is
developed across the r DS(ON) of each lower MOSFET, while
they are conducting. A single resistor converts and scales
the voltage across the MOSFETs to a current that is applied
to the Current Sensing circuit within the ISL6315. Output
from these sensing circuits is applied to the current
averaging circuit. Each PWM channel receives the
difference current signal from the summing circuit that
compares the average sensed current to the individual
channel current. When a power channel’s current is greater
than the average current, the signal applied via the summing
Correction circuit to the Comparator, reduces the output
pulse width of the Comparator to compensate for the
detected “above average” current in that channel.
MULTIPHASE POWER CONVERSION
Multiphase power conversion provides a cost-effective
power solution when load currents are no longer easily
supported by single-phase converters. Although its greater
complexity presents additional technical challenges, the
multiphase approach offers cost-saving advantages with
improved response time, superior ripple cancellation, and
thermal distribution.
DAC
&
OSCILLATOR
V IN
REFERENCE
UGATE1
COMP
Σ
PWM
CIRCUIT
HALF-BRIDGE
DRIVE
LGATE1
R2
L1
C2
Σ
PWM
CIRCUIT
HALF-BRIDGE
DRIVE
PHASE1
V OUT
ERROR
FB
AMP
Σ
CURRENT
SENSE
V IN
L2
C OUT
R1
AVERAGE
UGATE2
Σ
CURRENT
SENSE
LGATE2
PHASE2
ISL6315
ISEN
R ISEN
VCC
FIGURE 1. SIMPLIFIED BLOCK DIAGRAM OF THE ISL6315 VOLTAGE AND CURRENT FEEDBACK
7
FN9222.1
July 18, 2007
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